Design and Implementation of RNS-Based Adaptive Filters

  • Javier Ramírez
  • Uwe Meyer-Bäse
  • Antonio García
  • Antonio Lloris
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This paper presents the residue number system (RNS) implementation of reduced complexity and high performance adaptive FIR filters on Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields along with a selection of a small wordwidth modulus set are keys for attaining low-complexity and high-throughput. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage improved area requirements by 10% for a 32-tap FIR filter. A block LMS (BLMS) implementation was preferred for the update of the adaptive FIR filter coefficients. RNS-FPL merged filters demonstrated its superiority when compared to 2C (two’s complement) filters, being about 65% faster and requiring fewer logic elements for most study cases.


Residue Number System VLSI Signal Processing Galois Field Move Target Detection Binary Adder 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Szabo, N.S., Tanaka, R.I.: Residue Arithmetic and its Applications to Computer Technology. McGraw-Hill, New York (1967)zbMATHGoogle Scholar
  2. 2.
    Soderstrand, M., Jenkins, W., Jullien, G.A., Taylor, F.J.: Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Computer Society Press, Los Alamitos (1986)zbMATHGoogle Scholar
  3. 3.
    Ramírez, J., Meyer-Bäse, U., Taylor, F., García, A., Lloris, A.: Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. Journal of VLSI Signal Processing 34, 227–237 (2003)CrossRefGoogle Scholar
  4. 4.
    Ramírez, J., García, A., Meyer-Bäse, U., Lloris, A.: Fast RNS-based FPL Communications Receiver Design and Implementation. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 472–481. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  5. 5.
    Hamann, V., Sprachmann, M.: Fast Residual Arithmetic with FPGAs. In: Workshop on Design Methodologies for Microelectronics (1995)Google Scholar
  6. 6.
    Safiri, H., Ahamadi, H., Jullien, G., Dimitrov, V.: Design of FPGA Implementation of Systolic FIR Filters Using Fermat Number ALU. In: Asilomar Conference on Signals, Systems and Computers, Pacific Grove (1997)Google Scholar
  7. 7.
    Meyer-Bäse, U., García, A., Taylor, F.: Implementation of a Communications Channelizer Using FPGAs and RNS Arithmetic. Journal of VLSI Signal Processing 28(1/2), 115–128 (2001)CrossRefGoogle Scholar
  8. 8.
    Jenkins, W.K., Schnaufer, B.A.: Fault tolerant adaptive filters based on the block LMS algorithm. 1993 IEEE International Symposium on Circuits and Systems 1, 862–865 (1993)CrossRefGoogle Scholar
  9. 9.
    Liu, C.M., Jen, C.W.: A parallel adaptive algorithm for moving target detection and its VLSI array realization. IEEE Transactions on Signal Processing 40(11), 2841–2848 (1992)CrossRefGoogle Scholar
  10. 10.
    Griffin, M., Sousa, M., Taylor, F.: Efficient Scaling in the Residue Number System. In: 1989 International Conference on Acoustics, Speech and Signal Processing, pp. 1075–1078 (1989)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Javier Ramírez
    • 1
  • Uwe Meyer-Bäse
    • 2
  • Antonio García
    • 1
  • Antonio Lloris
    • 1
  1. 1.Department of Electronics and Computer TechnologyUniversity of GranadaSpain
  2. 2.Department of Electrical and Computer EngineeringFAMU-FSU College of EngineeringUSA

Personalised recommendations