Track Placement: Orchestrating Routing Structures to Maximize Routability
The design of a routing channel for an FPGA is a complex process requiring a careful balance of flexibility with silicon efficiency. With a growing move towards embedding FPGAs into SoC designs, and the new opportunity to automatically generate FPGA architectures, this problem is even more critical. The design of a routing channel requires determining the number of routing tracks, the length of the wires in those tracks, and the positioning of the breaks between wires on the tracks. This paper focuses on the last problem, the placement of breaks in tracks to maximize overall flexibility. Our optimal algorithm for track placement finds a best solution provided the problem meets a number of restrictions. Our relaxed algorithm is without restrictions, and finds solutions on average within 1.13% of optimal.
KeywordsDiversity Score Track Length Signal Length Wire Length Local Track
Unable to display preview. Download preview PDF.
- 1.Compton, K., Hauck, S.: Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. In: International Conference on Field-Programmable Logic and Applications, pp. 59–68 (2002)Google Scholar
- 2.Cronquist, D.C., Franklin, P., Fisher, C., Figueroa, M., Ebeling, C.: Architecture Design of Reconfigurable Pipelined Datapaths. In: Twentieth Anniversary Conference on Advanced Research in VLSI (1999)Google Scholar
- 3.Hauser, J.R.: The Garp Architecture., University of California at Berkeley Technical Report (1997)Google Scholar
- 4.Betz, V., Rose, J.: Automatic Generation of FPGA Routing Architectures from High-Level Descriptions. In: ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 175–184 (2000)Google Scholar
- 5.Compton, K., Hauck, S.: Track Placement: Orchestrating Routing Structures to Maximize Routability, University of Washington Technical Report UWEETR-2002-0013 (2002)Google Scholar