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FPGA Implementation of the Adaptive Lattice Filter

  • Antonín Heřmánek
  • Zdeněk Pohl
  • Jiří Kadlec
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

The paper presents the FPGA implementation of a noise canceler with an adaptive RLS-Lattice filter in the Xilinx devices. Since this algorithm requires floating-point computations, Logarithmic Numbering System (LNS) has been used. The pipelined lattice filter macro and input/output conversion routines has been designed. The implementation results are compared with an implementation on 32-bit IEEE floating point signal processor.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Antonín Heřmánek
    • 1
  • Zdeněk Pohl
    • 1
  • Jiří Kadlec
    • 1
  1. 1.Department of Signal ProcessingInstitute of Information Theory and Automation, CASPrague 8Czech Republic

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