FPGA Implementation of the Adaptive Lattice Filter
The paper presents the FPGA implementation of a noise canceler with an adaptive RLS-Lattice filter in the Xilinx devices. Since this algorithm requires floating-point computations, Logarithmic Numbering System (LNS) has been used. The pipelined lattice filter macro and input/output conversion routines has been designed. The implementation results are compared with an implementation on 32-bit IEEE floating point signal processor.
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- 6.Coleman, J.N., Chester, E.I.: A 32b Logarithmic Number System Processor and Its Performance Compared to Floating Point. In: Proc. 14th IEEE Symposium on Computer Arithmetic, Adelaide, April 1999, pp. 142–152 (1999)Google Scholar