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Hardware-Software Codesign in Embedded Asymmetric Cryptography Application – A Case Study

  • Martin Šimka
  • Viktor Fischer
  • Miloš Drutarovský
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper presents a case study of a hardware-software codesign of the RSA cipher embedded in reconfigurable hardware. The soft cores of Altera’s Nios RISC processor are used as the basic building block of the proposed complete embedded solutions. The effect of moving computationally intensive parts of RSA into an optimized parameterized scalable Montgomery coprocessor(s) is analyzed and compared with a pure software solution. The impact of the tasks distribution between the hardware and the software on the occupation of logic resources as well as the speed of the algorithm is demonstrated and generalized.

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References

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    Menezes, J.A., Oorschot, P.C., Vanstone, S.A.: Applied Cryptography. CRC Press, New York (1997)zbMATHGoogle Scholar
  2. 2.
    Tenca, A.F., Koc, C.K.: A scalable architecture for Montgomery multiplication. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 94–108. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  3. 3.
    Šimka, M., Fischer, V.: Montgomery Multiplication Coprocessor for Altera Nios Embedded Processor. In: Proceedings of the 5th International Scientific Conference on Electronic Computers and Informatics 2002, Kosice, Slovakia, October 2002, pp. 206–211 (2002)Google Scholar
  4. 4.
    Nios Soft Core Embedded processor, www.altera.com/nios

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Martin Šimka
    • 1
  • Viktor Fischer
    • 2
  • Miloš Drutarovský
    • 1
  1. 1.Department of Electronics and Multimedia CommunicationsTechnical University of KošiceKošiceSlovakia
  2. 2.Laboratoire Traitement du Signal et Instrumentation, Unité Mixte de Recherche CNRS 5516Université Jean MonnetSaint-EtienneFrance

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