FPGA Implementation of Multi-layer Perceptrons for Speech Recognition
In this work we present different hardware implementations of a multi-layer perceptron for speech recognition. The designs have been defined using two different abstraction levels: register transfer level (VHDL) and a higher algorithmic-like level (Handel-C). The implementations have been developed and tested into a reconfigurable hardware (FPGA) for embedded systems. A study of the two considered approaches costs (silicon area), speed and required computational resources is presented.
KeywordsSpeech Recognition Parallel Version High Level Description FPGA Implementation Register Transfer Level
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