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A VHDL Library to Analyse Fault Tolerant Techniques

  • P. M. Ortigosa
  • O. López
  • R. Estrada
  • I. García
  • E. M. Garzón
Conference paper
  • 1.1k Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This work presents an initiative to teach the basis of fault tolerance in digital systems design in undergraduate and graduate courses in electrical and computer engineering. The approach is based on a library of characteristic circuits related to fault tolerance techniques which has been implemented using a Hardware Description Language (VHDL). Due to the properties of the design tools associated to these languages, this approach allows with ease: (1) to implement faults tolerant digital systems; (2) to d etermine the behaviour of system when faults are presented; (3) to evaluate the additional resources and response time linked to any fault tolerance technique in the laboratory.

Keywords

Fault Detector Digital System Cyclic Code Arithmetic Code Hardware Redundancy 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • P. M. Ortigosa
    • 1
  • O. López
    • 1
  • R. Estrada
    • 1
  • I. García
    • 1
  • E. M. Garzón
    • 1
  1. 1.Dpt. of Computer Architecture and ElectronicsUniversity of AlmeríaAlmeríaSpain

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