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Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms

  • K. Tatas
  • K. Siozios
  • D. Soudris
  • A. Thanailakis
Conference paper
  • 1.1k Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

The power-efficient implementation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. Comparisons among implementations with and without this optimization, prove that great power efficiency is achieved while satisfying performance constraints.

Keywords

Multimedia Application External Memory Total Power Consumption Memory Hierarchy Motion Estimation Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • K. Tatas
    • 1
  • K. Siozios
    • 1
  • D. Soudris
    • 1
  • A. Thanailakis
    • 1
  1. 1.VLSI Design and Testing Center, Department of Electrical and Computer EngineeringDemocritus University of ThraceXanthiGreece

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