FPGA Implementations of the RC6 Block Cipher

  • Jean-Luc Beuchat
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


RC6 is a symmetric-key algorithm which encrypts 128-bit plaintext blocks to 128-bit ciphertext blocks. The encryption process involves four operations: integer addition modulo 2w, bitwise exclusive or of two w-bit words, rotation to the left, and computation of f(X)=(X (2X+1)) mod 2w, which is the critical arithmetic operation of this block cipher. In this paper, we investigate and compare four implementations of the f(X) operator on Virtex-E and Virtex-II devices. Our experiments show that the choice of an algorithm is strongly related to the target FPGA family. We also describe several architectures of a RC6 processor designed for feedback or non-feedback chaining modes. Our fastest implementation achieves a throughput of 15.2 Gb/s on a Xilinx XC2V3000-6 device.


Block Cipher Advance Encryption Standard Pipeline Stage FPGA Implementation Loop Unroll 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Beuchat, J.-L.: Etude et conception d’opérateurs arithmétiques optimisës pour circuits programmables. PhD thesis, Swiss Federal Institute of Technology Lausanne (2001)Google Scholar
  2. 2.
    Chodowiec, P., Khuon, P., Gaj, K.: Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round Pipelining. In: Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 94–102 (2001)Google Scholar
  3. 3.
    Dworkin, M.: Recommandation for Block Cipher Modes of Operation. NIST Special Publication 800-38A (2001)Google Scholar
  4. 4.
    Gaj, K., Chodowiec, P.: Fast implementation and fair comparison of the final candidates for Advanced Encryption Standard using Field Programmable Gate Arrays. In: Naccache, D. (ed.) CT-RSA 2001. LNCS, vol. 2020, pp. 84–99. Springer, Heidelberg (2001), Available at
  5. 5.
    Lipmaa, H., Rogaway, P., Wagner, D.: Comments to NIST concerning AES Modes of Operations: CTR-Mode EncryptionGoogle Scholar
  6. 6.
    Menezes, A.J., van Oorschot, P.C., Vanstone, S.A.: Handbook of Applied Cryptography. CRC Press, Boca Raton (1997)zbMATHGoogle Scholar
  7. 7.
    Mosanya, E., Teuscher, C., Restrepo, H.F., Galley, P., Sanchez, E.: Crypto-Booster: A Reconfigurable and Modular Cryprographic Coprocessor. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 246–256. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  8. 8.
    Parhami, B.: Computer Arithmetic. Oxford University Press, Oxford (2000)Google Scholar
  9. 9.
    Rivest, R.L., Robshaw, M.J.B., Sidney, R., Yin, Y.L.: The RC6 Block Cipher (1998)Google Scholar
  10. 10.
    Weeks, B., Bean, M., Rozylowicz, T., Ficke, C.: Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms. Technical report, National Security Agency (2000)Google Scholar
  11. 11.
    Zimmermann, R., Curiger, A., Bonnenberg, H., Kaeslin, H., Felber, N., Fichtner, W.: A 177 Mbit/s VLSI Implementation of the International Data Encryption Algorithm. IEEE Journal of Solid-State Circuits 29(3), 303–307 (1994)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jean-Luc Beuchat
    • 1
  1. 1.Laboratoire de l’Informatique du ParallélismeEcole Normale Supérieure de LyonLyon Cedex 07France

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