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FPGA Implementations of the RC6 Block Cipher

  • Jean-Luc Beuchat
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

RC6 is a symmetric-key algorithm which encrypts 128-bit plaintext blocks to 128-bit ciphertext blocks. The encryption process involves four operations: integer addition modulo 2w, bitwise exclusive or of two w-bit words, rotation to the left, and computation of f(X)=(X (2X+1)) mod 2w, which is the critical arithmetic operation of this block cipher. In this paper, we investigate and compare four implementations of the f(X) operator on Virtex-E and Virtex-II devices. Our experiments show that the choice of an algorithm is strongly related to the target FPGA family. We also describe several architectures of a RC6 processor designed for feedback or non-feedback chaining modes. Our fastest implementation achieves a throughput of 15.2 Gb/s on a Xilinx XC2V3000-6 device.

Keywords

Block Cipher Advance Encryption Standard Pipeline Stage FPGA Implementation Loop Unroll 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jean-Luc Beuchat
    • 1
  1. 1.Laboratoire de l’Informatique du ParallélismeEcole Normale Supérieure de LyonLyon Cedex 07France

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