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FPGA Implementation of Adaptive Non-linear Predictors for Video Compression

  • Rafael Gadea-Girones
  • Agustín Ramirez-Agundis
  • Joaquín Cerdá-Boluda
  • Ricardo Colom-Palero
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

The paper describes the implementation of a systolic array for a non-linear predictor for image compression. We can implement very large interconnection layers by using large Xilinx and Altera devices with embedded memories and multipliers alongside the projection used in the systolic architecture. These physical and architectural features create a reusable, flexible, and fast method of designing a complete ANN (Artificial Neural Networks) on FPGAs. Our predictor, a MLP (Multilayer Perceptron) with the topology 12-10-1 and with training on the fly, works, both in recall and learning modes, with a throughput of 50 MHz, reaching the necessary speed for real-time training in video applications.

Keywords

Image Compression Systolic Array Learning Mode Video Compression Video Application 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Rafael Gadea-Girones
    • 1
  • Agustín Ramirez-Agundis
    • 2
  • Joaquín Cerdá-Boluda
    • 1
  • Ricardo Colom-Palero
    • 1
  1. 1.Department of Electronic EngineeringUniversidad Politécnica de ValenciaSpain
  2. 2.Department of Electronic EngineeringInstituto Tecnológico de CelayaAv. Tccnológico s/nMéxico

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