Configurable Hardware Architecture for Real-Time Window-Based Image Processing

  • Cesar Torres-Huitzil
  • Miguel Arias-Estrada
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


In this work, a configurable hardware architecture for window-based image operations for real-time applications is presented. The architecture is based on an array of elemental processors under a systolic and pipeline approach to achieve a high rate of processing. A configurable window processor has been developed to cover a broad class of image processing algorithms and operators. The system is modeled in a Hardware Description Language and has been prototyped on an FPGA device. Some implementation and performance results are presented and discussed.


Field Programmable Gate Array Hardware Architecture Hardware Resource Memory Bank Address Generator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Ranganathan, N.: VLSI & Parallel Computing for Pattern Recognition & Artificial Intelligence. Series in Machine Perception and Artificial Intelligence, vol. 18. World Scientific Publishing, Singapore (1995)CrossRefGoogle Scholar
  2. 2.
    Jain, R., Kasturi, R., Shunck, B.S.: Machine Vision, International Edition. McGraw-Hill, New York (1995)Google Scholar
  3. 3.
    Laplante, P.A., Stoyenko, A.D.: Real-time Imaging: Theory, Techniques, and Applications. IEEE Computer Society Press, Los Alamitos (1996)Google Scholar
  4. 4.
    Estrada, M.A., Huitzil, C.T.: Real-time Field Programmable Gate Array Architecture for Computer Vision. Journal of Electronic Imaging 10(1), 289–296 (2001)CrossRefGoogle Scholar
  5. 5.
    Kung, H.T.: Why systolic architectures?, January 1982, pp. 37–46. IEEE Computer Society Press, Los Alamitos (1982)Google Scholar
  6. 6.
    Pirsh, P., Stolberg, H.-J.: VLSI Implementations of Image and Video Multimedia Processing Systems. Transactions on Circuits and Systems for Video Technology 8(7), 878–891 (1998)CrossRefGoogle Scholar
  7. 7.
    Sweeney, C., Blyth, B.: RC1000-PP Hardware Reference Manual, Celoxica Limited, Version 1.22 (2000)Google Scholar
  8. 8.
    Siyal, M.Y., Fathy, M.: A Programmable Image Processor for Real-time Image Processing Applications. Microprocessors and Microsystems 23, 35–41 (1999)CrossRefGoogle Scholar
  9. 9.
    Ratha, N., Jain, A.: FPGA-based computing in Computer Vision. In: 4th IEEE International Workshop CAMP, pp. 128–137. IEEE Computer Society, Los Alamitos (1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Cesar Torres-Huitzil
    • 1
  • Miguel Arias-Estrada
    • 1
  1. 1.Computer Science DepartmentINAOEMéxico

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