Configurable Hardware Architecture for Real-Time Window-Based Image Processing
In this work, a configurable hardware architecture for window-based image operations for real-time applications is presented. The architecture is based on an array of elemental processors under a systolic and pipeline approach to achieve a high rate of processing. A configurable window processor has been developed to cover a broad class of image processing algorithms and operators. The system is modeled in a Hardware Description Language and has been prototyped on an FPGA device. Some implementation and performance results are presented and discussed.
KeywordsField Programmable Gate Array Hardware Architecture Hardware Resource Memory Bank Address Generator
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