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Configurable Hardware Architecture for Real-Time Window-Based Image Processing

  • Cesar Torres-Huitzil
  • Miguel Arias-Estrada
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this work, a configurable hardware architecture for window-based image operations for real-time applications is presented. The architecture is based on an array of elemental processors under a systolic and pipeline approach to achieve a high rate of processing. A configurable window processor has been developed to cover a broad class of image processing algorithms and operators. The system is modeled in a Hardware Description Language and has been prototyped on an FPGA device. Some implementation and performance results are presented and discussed.

Keywords

Field Programmable Gate Array Hardware Architecture Hardware Resource Memory Bank Address Generator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Cesar Torres-Huitzil
    • 1
  • Miguel Arias-Estrada
    • 1
  1. 1.Computer Science DepartmentINAOEMéxico

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