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A Statistical Analysis Tool for FPLD Architectures

  • Renqiu Huang
  • Tommy Cheung
  • Ted Kok
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper investigates an analysis tool for the routing resources in the FPLD architecture design. The developed tool can assess the performance of a given architecture specified by the physical configuration of logic blocks and the switch boxes topology. Two problems are mainly considered in this paper: given an architecture, the terminal distribution of each switch box is first determined via probabilistic assumptions, then the sizes of required universal switch boxes are evaluated for routing successfully. The estimations are validated by comp aring them with the results obtained in the previous published experimental study on FPGA benchmark circuits. Moreover, our result confirms that the universal switch block is a good candidate for FPLD design.

Keywords

Logic Block Develop Tool Statistical Analysis Tool Probabilistic Assumption Switch Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Renqiu Huang
    • 1
  • Tommy Cheung
    • 2
  • Ted Kok
    • 2
  1. 1.University of CincinnatiCincinnatiUSA
  2. 2.Hong Kong University of Science and TechnologyKowloon, HKSARChina

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