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FPGA Implementation of a Maze Routing Accelerator

  • John A. Nestor
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 X 16 single-layer and 4 X 4 multi-layer router that can handle 2-16 layers have been implemented in a low-end Xilinx XC2S300E FPGA. Larger arrays are currently under construction.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • John A. Nestor
    • 1
  1. 1.Department of Electrical and Computer EngineeringLafayette CollegeEastonUSA

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