Deductive Verification of Advanced Out-of-Order Microprocessors

  • Shuvendu K. Lahiri
  • Randal E. Bryant
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2725)

Abstract

This paper demonstrates the modeling and deductive verification of out-of-order microprocessors of varying complexities using a logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions (CLU). The microprocessors support combinations of out-of-order instruction execution, superscalar operation, branch prediction, execute and memory exceptions, and load-store buffering. We illustrate that the logic is expressive enough to model components found in modern processors. The paper describes the challenges in modeling and verification with the addition of different design features. The paper demonstrates the effective use of automatic decision procedure to reduce the amount of manual guidance required in discharging most proof obligations in the verification. Unlike previous methods, the verification scales well for superscalar processors with wide dispatch and retirement widths.

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References

  1. 1.
    Arons, T., Pnueli, A.: A comparison of two verification methods for speculative instruction execution. In: Schwartzbach, M.I., Graf, S. (eds.) TACAS 2000. LNCS, vol. 1785, p. 487. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  2. 2.
    Barrett, C., Dill, D., Levitt, J.: Validity checking for combinations of theories with equality. In: Srivas, M., Camilleri, A. (eds.) FMCAD 1996. LNCS, vol. 1166. Springer, Heidelberg (1996)CrossRefGoogle Scholar
  3. 3.
    Berezin, S., Biere, A., Clarke, E. M., Zhu, Y.: Combining symbolic model checking with uninterpreted functions for out-of-order processor verification. In: Gopalakrishnan, G.C., Windley, P. (eds.) FMCAD 1998. LNCS, vol. 1522, pp. 369–386. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  4. 4.
    Boyer, R.S., Moore, J.: A theorem prover for a computational logic. In: Stickel, M.E. (ed.) CADE 1990. LNCS, vol. 449. Springer, Heidelberg (1990)Google Scholar
  5. 5.
    Bryant, R.E., German, S., Velev, M.N.: Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic 2(1), 1–41 (2001)CrossRefMathSciNetGoogle Scholar
  6. 6.
    Bryant, R.E., Lahiri, S.K., Seshia, S.A.: Modeling and verifying systems using a logic of counter arithmetic with lambda expressions and uninterpreted functions. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, p. 78. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  7. 7.
    Burch, J.R., Dill, D.L.: Automated verification of pipelined microprocessor control. In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818, pp. 68–80. Springer, Heidelberg (1994)Google Scholar
  8. 8.
    Gurevich, Y.: The decision problem for standard classes. The Journal of Symbolic Logic 41(2), 460–464 (1976)MATHCrossRefMathSciNetGoogle Scholar
  9. 9.
    Hosabettu, R., Gopalakrishnan, G., Srivas, M.: Verifying advanced microarchitectures that support speculation and exceptions. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  10. 10.
    Jhala, R., McMillan, K.: Microarchitecture verification by compositional model checking. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, p. 396. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  11. 11.
    Lahiri, S.K., Seshia, S.A., Bryant, R.E.: Modeling and verification of out-oforder microprocessors in UCLID. In: Aagaard, M.D., O’Leary, J.W. (eds.) FMCAD 2002. LNCS, vol. 2517, pp. 142–159. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  12. 12.
    Owre, S., Rushby, J.M., Shankar, N.: PVS: A prototype verification system. In: 11th International Conference on Automated Deduction (CADE) (June 1992)Google Scholar
  13. 13.
    Sawada, J., Hunt, W.: Processor verification with precise exceptions and speculative execution. In: Y. Vardi, M. (ed.) CAV 1998. LNCS, vol. 1427. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  14. 14.
    Skakkaebaek, J.U., Jones, R.B., Dill, D.L.: Formal verification of out-of-order execution using incremental flushing. In: Y. Vardi, M. (ed.) CAV 1998. LNCS, vol. 1427. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  15. 15.
    Velev, M.N.: Using rewriting rules and positive equality to formally verify wideissue out-of-order microprocessors with a reorder buffer. In: Design, Automation and Test in Europe (DATE 2002), pp. 28–35 (March 2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Shuvendu K. Lahiri
    • 1
  • Randal E. Bryant
    • 1
  1. 1.Carnegie Mellon UniversityPittsburgh

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