Rabbit: A Tool for BDD-Based Verification of Real-Time Systems

  • Dirk Beyer
  • Claus Lewerentz
  • Andreas Noack
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2725)


This paper gives a short overview of a model checking tool for real-time systems. The modeling language are timed automata extended with concepts for modular modeling. The tool provides reachability analysis and refinement checking, both implemented using the data structure BDD. Good variable orderings for the BDDs are computed from the modular structure of the model and an estimate of the BDD size. This leads to a significant performance improvement compared to the tool RED and the BDD-based version of Kronos.


Reachability Analysis Model Check Tool Clock Constraint Time Automaton Model Mutual Exclusion Property 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Alur, R., Dill, D.L.: A theory of timed automata. Theoretical Computer Science 126, 183–235 (1994)zbMATHCrossRefMathSciNetGoogle Scholar
  2. 2.
    Amnell, T., Behrmann, G., Bengtsson, J., D’Argenio, P.R., David, A., Fehnker, A., Hune, T., Jeannet, B., Larsen, K.G., Möller, M.O., Pettersson, P., Weise, C., Yi, W.: Uppaal - now, next, and future. In: Cassez, F., Jard, C., Rozoy, B., Dermot, M. (eds.) MOVEP 2000. LNCS, vol. 2067, pp. 99–124. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  3. 3.
    Beyer, D.: Improvements in BDD-based Reachability Analysis of Timed Automata. In: Oliveira, J.N., Zave, P. (eds.) FME 2001. LNCS, vol. 2021, pp. 318–343. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  4. 4.
    Beyer, D.: Efficient Reachability Analysis and Refinement Checking of Timed Automata using BDDs. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 86–91. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  5. 5.
    Beyer, D.: Formale Verifikation von Realzeit-Systemen mittels Cottbus Timed Automata. Verlag Mensch & Buch, Berlin, 2002. Zugl.: Dissertation, BTU Cottbus (2002)Google Scholar
  6. 6.
    Beyer, D., Noack, A.: A comparative study of decision diagrams for real-time verification. Technical Report I-03/2003, BTU Cottbus (2003)Google Scholar
  7. 7.
    Beyer, D., Rust, H.: Cottbus Timed Automata: Formal Definition and Semantics. In: Proc. FSCBS 2001, pp. 75–87 (2001)Google Scholar
  8. 8.
    Bozga, M., Maler, O., Pnueli, A., Yovine, S.: Some progress on the symbolic verification of timed automata. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, pp. 179–190. Springer, Heidelberg (1997)Google Scholar
  9. 9.
    Burch, J.R., Clarke, E.M., Long, D.E., McMillan, K.L., Dill, D.L.: Symbolic model checking for sequential circuit verification. IEEE Transactions on CAD 13(4), 401–424 (1994)Google Scholar
  10. 10.
    Wang, F.: Symbolic verification of complex real-time systems with clock-restriction diagram. In: Proc. FORTE 2001, pp. 235–250. Kluwer, Dordrecht (2001)Google Scholar
  11. 11.
    Yovine, S.: Kronos: A verification tool for real-time systems. Software Tools for Technology Transfer 1(1-2), 123–133 (1997)zbMATHCrossRefGoogle Scholar
  12. 12.
    Yovine, S.: Model checking timed automata. In: Rozenberg, G. (ed.) EEF School 1996. LNCS, vol. 1494, pp. 114–152. Springer, Heidelberg (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Dirk Beyer
    • 1
  • Claus Lewerentz
    • 1
  • Andreas Noack
    • 1
  1. 1.Software Systems Engineering Research GroupBrandenburg Technical University at CottbusGermany

Personalised recommendations