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Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing

  • Jürgen Fischer
  • Ettore Amirante
  • Francesco Randazzo
  • Giuseppe Iannaccone
  • Doris Schmitt-Landsiedel
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

Positive Feedback Adiabatic Logic (PFAL) with minimal dimensioned transistors can save energy compared to static CMOS up to an operating frequency f = 200MHz. In this work the impact of transistor sizing is discussed, and design rules are analytically derived and confirmed by simulations. The increase of the p-channel transistor width can significantly reduce the resistance of the charging path decreasing the energy dissipation of the PFAL inverter by a factor of 2. In more complex gates a further design rule for the sizing of the n-channel transistors is proposed. Simulations of a PFAL 1-bit full adder show that the energy consumption can be reduced by additional 10% and energy savings can be achieved beyond f = 1GHz in a 0.13μm CMOS technology. The results are validated through the use of the design centering tool ‘WiCkeD’ [1].

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jürgen Fischer
    • 1
  • Ettore Amirante
    • 1
  • Francesco Randazzo
    • 2
  • Giuseppe Iannaccone
    • 2
  • Doris Schmitt-Landsiedel
    • 1
  1. 1.Institute for Technical ElectronicsTechnical University MunichMunichGermany
  2. 2.Dipartimento di Ingegneria dell’InformazioneUniversità degli Studi di PisaPisaItaly

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