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Instruction Level Energy Modeling for Pipelined Processors

  • S. Nikolaidis
  • N. Kavvadias
  • T. Laopoulos
  • L. Bisdounis
  • S. Blionas
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)

Abstract

A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.

Keywords

Clock Cycle Very Large Scale Inte Pipeline Stage Instantaneous Current Base Cost 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • S. Nikolaidis
    • 1
  • N. Kavvadias
    • 1
  • T. Laopoulos
    • 1
  • L. Bisdounis
    • 2
  • S. Blionas
    • 2
  1. 1.Department of PhysicsAristotle University of ThessalonikiThessalonikiGreece
  2. 2.INTRACOM S.A.PeaniaGreece

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