Using Split Queues to Improve the Performance of Parallel Switch
Parallel switch scales well with the growth of port density and line rate. PSIQC (Parallel Switch based on Input-Queued Crossbar) is a parallel switch that is scalable and simple to implement. But it needs large capacity high-speed memories to store cells, and the average cell latency is high under heavy load. This paper presents a revised version of PSIQC based on split queues that is initialed as SQ-PSIQC (Split Queued Parallel Switch based on Input-Queued Crossbar), and its scheduling algorithm SQ-RRDS (Split Queued Round Robin and Deterministic Sequence). SQ-PSIQC not only has all of the original characteristics, but also solves the two above-mentioned problems. In SQ-PSIQC the memory buffers are required to operate only at 1/m of the line rate, where m is the number of the middle switches. The simulation results show that SQ-PSIQC performs better than PSIQC in the average latency and throughput under any load, especially heavy load.
KeywordsTime Slot Output Port Heavy Load Input Port Switch Module
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- 1.McKeown, N.: A fast switched backplane for a gigabit switched router. Business Communications Review (December 1997)Google Scholar
- 4.Arpaci, M., Copeland, J.: Buffer Management for Shared-Memory ATM Switches. IEEE Communications Surveys, 1Q (2000)Google Scholar
- 5.Semeria, C.: Internet backbone routers and evolving Internet design. White paper, http://www.juniper.com
- 6.Iyer, S., Zhang, R., McKeown, N.: Routers with a Single Stage of Buffering. In: Proc. of ACM SIGCOMM 2002, Pittsburgh (September 2002)Google Scholar
- 7.Iyer, S., Awadallah, A., McKeown, N.: Analysis of a packet switch with memories running slower than the line rate. In: Proc. of IEEE Infocom 2000, Tel-Aviv, Israel (March 2000)Google Scholar
- 8.Iyer, S., McKeown, N.: Making Parallel Packet Switches Practical. In: Proc. of IEEE Infocom 2001, Alaska (April 2001)Google Scholar
- 9.Wang, W., Dong, L., Wolf, W.: A Distributed Switch Architecture with Dynamic Loadbalancing and Parallel Input-Queued Crossbars for Terabit Switch Fabrics. In: Proc. Of IEEE Infocom 2002, New York (June 2002)Google Scholar
- 10.Keslassy, I., McKeown, N.: Maintaining Packet Order in Two-Stage Switches. In: Proc. of IEEE Infocom 2002, New York (June 2002)Google Scholar
- 11.Chiussi, F., Khotimsky, D., Krishnan, S.: Generalized Inverse Multiplexing of Switched ATM Connections. In: Proc. of IEEE Globecom 1998, Sydney, Australia (November 1998)Google Scholar
- 14.Zhigang, S., Jinshu, S., Xicheng, L.: ISP: a high performance crossbar arbitrating algorithm. Journal of Computer Research and Development (In Chinese) 23(10), 1078–1082 (2000)Google Scholar