Advertisement

Optimizing Bounded Model Checking for Linear Hybrid Systems

  • Erika Ábrahám
  • Bernd Becker
  • Felix Klaedtke
  • Martin Steffen
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3385)

Abstract

Bounded model checking (BMC) is an automatic verification method that is based on finitely unfolding the system’s transition relation. BMC has been successfully applied, in particular, for discovering bugs in digital system design. Its success is based on the effectiveness of satisfiability solvers that are used to check for a finite unfolding whether a violating state is reachable. In this paper we improve the BMC approach for linear hybrid systems. Our improvements are tailored to lazy satisfiability solving and follow two complementary directions. First, we optimize the formula representation of the finite unfoldings of the transition relations of linear hybrid systems, and second, we accelerate the satisfiability checks by accumulating and generalizing data that is generated during earlier satisfiability checks. Experimental results show that the presented techniques accelerate the satisfiability checks significantly.

Keywords

Model Check Boolean Variable Satisfying Assignment Hybrid Automaton Boolean Combination 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Ábrahám, E., Becker, B., Klaedtke, F., Steffen, M.: Optimizing bounded model checking for linear hybrid systems. Technical Report TR214, Albert-Ludwigs-Universität Freiburg, Fakultät für Angewandte Wissenschaften, Institut für Informatik (2004), Online, available at http://www.informatik.uni-freiburg.de/tr/
  2. 2.
    Alur, R., Courcoubetis, C., Henzinger, T., Ho, P.-H., Nicollin, X., Olivero, A., Sifakis, J., Yovine, S.: The algorithmic analysis of hybrid systems. Theor. Comput. Sci. 138, 3–34 (1995)MATHCrossRefGoogle Scholar
  3. 3.
    Alur, R., Dill, D.: A theory of timed automata. Theor. Comput. Sci. 126, 183–235 (1994)MATHCrossRefMathSciNetGoogle Scholar
  4. 4.
    Alur, R., Henzinger, T., Ho, P.-H.: Automatic symbolic verification of embedded systems. IEEE Transactions on Software Engineering 22, 181–201 (1996)CrossRefGoogle Scholar
  5. 5.
    Audemard, G., Bertoli, P., Cimatti, A., Korniłowicz, A., Sebastiani, R.: A SAT based approach for solving formulas over boolean and linear mathematical propositions. In: Voronkov, A. (ed.) CADE 2002. LNCS (LNAI), vol. 2392, pp. 195–210. Springer, Heidelberg (2002)Google Scholar
  6. 6.
    Audemard, G., Bozzano, M., Cimatti, A., Sebastiani, R.: Verifying industrial hybrid systems with MathSAT. In: Proc. of BMC 2004 (2004)Google Scholar
  7. 7.
    Audemard, G., Cimatti, A., Korniłowicz, A., Sebastiani, R.: Bounded model checking for timed systems. In: Peled, D.A., Vardi, M.Y. (eds.) FORTE 2002. LNCS, vol. 2529, pp. 243–259. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  8. 8.
    Barrett, C., Berezin, S.: CVC Lite: A new implementation of the cooperating validity checker. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 515–518. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  9. 9.
    Biere, A., Cimatti, A., Clarke, E., Strichman, O., Zhu, Y.: Bounded model checking. Advances in Computers 58 (2003)Google Scholar
  10. 10.
    Biere, A., Cimatti, A., Clarke, E., Zhu, Y.: Symbolic model checking without BDDs. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, pp. 193–207. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  11. 11.
    Biere, A., Clarke, E., Raimi, R., Zhu, Y.: Verifying safety properties of a powerPCTM microprocessor using symbolic model checking without BDDs. In: Halbwachs, N., Peled, D.A. (eds.) CAV 1999. LNCS, vol. 1633, pp. 60–71. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  12. 12.
    Clarke, E., Emerson, E.: Design and synthesis of synchronisation skeletons using branching time temporal logic specifications. In: Kozen, D. (ed.) Logic of Programs 1981. LNCS, vol. 131, pp. 244–263. Springer, Heidelberg (1982)Google Scholar
  13. 13.
    Copty, F., Fix, L., Fraer, R., Giunchiglia, E., Kamhi, G., Tacchella, A., Vardi, M.Y.: Benefits of bounded model checking at an industrial setting. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, pp. 436–453. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  14. 14.
    de Moura, L., Rueß, H.: Lemmas on demand for satisfiability solvers. In: Proc. of SAT 2002, pp. 244–251 (2002)Google Scholar
  15. 15.
    de Moura, L., Rueß, H.: An experimental evaluation of ground decision procedures. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 162–174. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  16. 16.
    de Moura, L., Rueß, H., Sorea, M.: Lazy theorem proving for bounded model checking over infinite domains. In: Voronkov, A. (ed.) CADE 2002. LNCS (LNAI), vol. 2392, pp. 438–455. Springer, Heidelberg (2002)Google Scholar
  17. 17.
    de Moura, L., Rueß, H., Sorea, M.: Bounded model checking and induction: From refutation to verification. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 14–26. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  18. 18.
    Henzinger, T.: The theory of hybrid automata. In: Proc. of LICS 1996, pp. 278–292 (1996)Google Scholar
  19. 19.
    Niebert, P., Mahfoudh, M., Asarin, E., Bozga, M., Maler, O., Jain, N.: Verification of timed automata via satisfiability checking. In: Damm, W., Olderog, E.-R. (eds.) FTRTFT 2002. LNCS, vol. 2469, pp. 225–244. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  20. 20.
    Queille, J., Sifakis, J.: Specification and verification of concurrent systems in CESAR. In Proc. of the 5th International Symposium on Programming 1981. In: Dezani-Ciancaglini, M., Montanari, U. (eds.) Programming 1982. LNCS, vol. 137, pp. 337–351. Springer, Heidelberg (1982)Google Scholar
  21. 21.
    Sheeran, M., Singh, S., Stålmarck, G.: Checking safety properties using induction and a SAT-solver. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 108–125. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  22. 22.
    Sorea, M.: Bounded model checking for timed automata. Electronic Notes in Theoretical Computer Science 68 (2002)Google Scholar
  23. 23.
    Strichman, O.: Accelerating bounded model checking of safety properties. Formal Methods in System Design 24(1), 5–24 (2004)MATHCrossRefGoogle Scholar
  24. 24.
    Tarski, A.: A Decision Method for Elementary Algebra and Geometry, 2nd edn. University of California Press, Berkeley (1951)MATHGoogle Scholar
  25. 25.
    Woźna, B., Zbrzezny, A., Penczek, W.: Checking reachability properties for timed automata via SAT. Fundamenta Informaticae 55(2), 223–241 (2003)MATHMathSciNetGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Erika Ábrahám
    • 1
  • Bernd Becker
    • 1
  • Felix Klaedtke
    • 2
  • Martin Steffen
    • 3
  1. 1.Albert-Ludwigs-Universität FreiburgGermany
  2. 2.ETH ZurichSwitzerland
  3. 3.Christian-Albrechts-Universität zu KielGermany

Personalised recommendations