A New Logic Transformation Method for Both Low Power and High Testability

  • Y. S. Son
  • J. W. Na
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3254)


An efficient logic transformation method to achieve both low power consumption and high testability is proposed in this paper. The proposed method is based on the redundancy insertion and removal approach. It is also described how redundant connections operate as test points in the test mode. The results of experiments on MCNC benchmark circuits show that the transformed circuit consumes less power in the normal mode and has higher testability in the test mode than the original.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Y. S. Son
    • 1
  • J. W. Na
    • 2
  1. 1.Waytotec, IncSung Nam Si, Gyung Gi DoSouth Korea
  2. 2.Computer Engineering DeptHansei UniversityGyung Gi DoSouth Korea

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