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A New Logic Transformation Method for Both Low Power and High Testability

  • Y. S. Son
  • J. W. Na
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3254)

Abstract

An efficient logic transformation method to achieve both low power consumption and high testability is proposed in this paper. The proposed method is based on the redundancy insertion and removal approach. It is also described how redundant connections operate as test points in the test mode. The results of experiments on MCNC benchmark circuits show that the transformed circuit consumes less power in the normal mode and has higher testability in the test mode than the original.

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References

  1. 1.
    Rabaey, J.M., Pedram, M.: Low Power Design Methodologies, 1st edn. Kluwer Academic Publishers, Dordrecht (1996)Google Scholar
  2. 2.
    Rohfleisch, B., Kolbl, A., Wruth, B.: Reducing Power Dissipation after Technology Mapping by Structural Transformations. In: Proc. DAC, pp. 789–794 (1996)Google Scholar
  3. 3.
    Chang, S., et al.: Multilevel Boolean Network Optimizer. IEEE Trans. CAD 15(12), 1494–1504 (1996)Google Scholar
  4. 4.
    Cheng, K.T., Entrena, L.A.: Multi-level Logic Optimization By Redundancy Addition and Removal. In: Proc. European DAC, pp. 373–337 (1993)Google Scholar
  5. 5.
    Wang, Q., Vrudhula, S.B.: Multi-level Logic Optimization for Low Power using Local Logic Transformations. In: Proc. ICCAD, pp. 270–277 (1996)Google Scholar
  6. 6.
    Chung, K.-S., Liu, C.L.: Local Transformation Techniques for Multi-Level Logic Circuits Utilizing Circuit Symmetries for Power Reductions. In: Proc. ISLPED, pp. 215–220 (1998)Google Scholar
  7. 7.
    Savir, J., Berry, R.: At-speed test is not necessarily an AC test. In: Proc. ITC, pp. 722–728 (1991)Google Scholar
  8. 8.
    Chaterjee, M., Pradhan, D.K.: A Novel Pattern Generator for Near-Perfect Fault-Coverage. In: Proc. VLSI Test Symp., pp. 417–425 (1995)Google Scholar
  9. 9.
    Savir, J.: Reducing the MISR size. IEEE Trans. Comp. 45, 930–938 (1996)MATHCrossRefGoogle Scholar
  10. 10.
    AlShaibi, M.F., Kime, C.R.: MFBIST: A BIST Method for Random Pattern Resistant Circuits. In: Proc. ITC, pp. 176–185 (1996)Google Scholar
  11. 11.
    Bardell, P.H., McAnney, W.H., Savir, J.: Built-In Test for VLSI: Pseudorandom Techniques, 1st edn. John Wiley & Sons, Chichester (1987)Google Scholar
  12. 12.
    Goldstein, H.: Controllability/observability of digital circuits. IEEE Trans. Circuits and Systems, 685–693 (1979)Google Scholar
  13. 13.
    Costa, J.C., Monteiro, J.C., Devadas, S.: Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In: Proc. ISLPED, pp. 184–189 (1997)Google Scholar
  14. 14.
    Lee, H.K., Ha, D.S.: Atalanta: an Efficient ATPG for Combinational Circuits, Technical Report, pp. 93-12, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University (1993)Google Scholar
  15. 15.
    Lee, H.K., Ha, D.S.: An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation. In: Proc. ITC, pp. 946–955 (1991)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Y. S. Son
    • 1
  • J. W. Na
    • 2
  1. 1.Waytotec, IncSung Nam Si, Gyung Gi DoSouth Korea
  2. 2.Computer Engineering DeptHansei UniversityGyung Gi DoSouth Korea

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