Advertisement

Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors

  • Nikolaos Kavvadias
  • Spiridon Nikolaidis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3254)

Abstract

An extensible and configurable processor is a programmable platform offering the possibility to customize the instruction set and/or underlying microarchitecture. Efficient application analysis can identify the application parameters and instruction extensions that would influence processor performance. An application characterization flow is presented and demonstrated on the Wavelet/Scalar Quantization image compression application. In this context, novel application metrics are identified as the percentage cover, maximum cycle gain for each basic block and candidate-induced application speedup due to possible complex instructions. Furthermore, evaluating the instruction candidates during application analysis is proposed in order to establish a link with subsequent design space exploration steps.

Keywords

Application Analysis Basic Block Intermediate Representation Data Flow Graph Instruction Extension 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Jacome, M.F., de Veciana, G.: Design challenges for new application-specific processors. IEEE Design and Test of Computers 17(2), 40–50 (2000)CrossRefGoogle Scholar
  2. 2.
    Gonzalez, R.: Xtensa: A configurable and extensible processor. IEEE Micro 20(2), 60–70 (2000)CrossRefGoogle Scholar
  3. 3.
    Altera Nios, http://www.altera.com
  4. 4.
    Gaisler research, http://www.gaisler.com
  5. 5.
    Itoh, M., Higaki, S., Sato, J., Shiomi, A., Takeuchi, Y., Kitajima, A., Imai, M.: PEAS-III: An ASIP design environment. In: IEEE Int. Conf. on Computer Design, pp. 430–436 (2000)Google Scholar
  6. 6.
    Hoffmann, A., et al.: A novel methodology for the design of application-specific instruction set processors (ASIPs) using a machine description language. IEEE Trans. on Computer- Aided Design 20(11), 1338–1354 (2001)CrossRefGoogle Scholar
  7. 7.
    Smith, M.D., Holloway, G.: An introduction to Machine SUIF and its portable libraries for analysis and optimization. Tech. Rpt., Division of Eng. and Applied Sciences, Harvard University, 2.02.07.15 edition (2002)Google Scholar
  8. 8.
    Gupta, T.V.K., Sharma, P., Balakrishnan, M., Malik, S.: Processor evaluation in an embedded systems design environment. In: 13th Int. Conf. on VLSI Design, pp. 98–103 (2000)Google Scholar
  9. 9.
    Ghazal, N., Newton, R., Rabaey, J.: Retargetable estimation scheme for DSP architecture selection. In: Asia and South Pacific Design Automation Conf., pp. 485–489 (2000)Google Scholar
  10. 10.
    Kim, S., Somani, A.K.: Characterization of an extended multimedia benchmark on a general purpose microprocessor architecture. Tech. Rpt DCNL-CA-2000-002, DCNL (2000)Google Scholar
  11. 11.
    Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A tool for evaluating and synthesizing multimedia and communication systems. In: Proc. of the IEEE/ACM Symp. on Microarchitecture, pp. 330–335 (1997)Google Scholar
  12. 12.
    Leupers, R., Wahlen, O., Hohenauer, M., Kogel, T., Marwedel, P.: An executable intermediate representation for retargetable compilation and high-level code optimization. In: Int. Wkshp. on Systems, Architectures, Modeling and Simulation (SAMOS), Samos, Greece (2003)Google Scholar
  13. 13.
    Clark, N., Zhong, H., Tang, W., Mahlke, S.: Automatic Design of Application Specific Instruction Set Extensions through Dataflow Graph Exploration. Int. Journal of Parallel Programming 31(6), 429–449 (2003)zbMATHCrossRefGoogle Scholar
  14. 14.
    Hopper, T., Brislawn, C., Bradley, J.: WSQ Greyscale Fingerprint Image Compression Specification, Version 2.0, Criminal Justice Information Services, FBI, Washington, DC (1993)Google Scholar
  15. 15.
    Kumar, S., Pires, L., Ponnuswamy, S., Nanavati, C., Golusky, V.M., Wadi, S., Pandalai, D., Spaanenburg, H.: A benchmark suite for evaluating configurable computing systems – Status, reflections, and future directions. In: ACM Int. Symp. on FPGAs (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Nikolaos Kavvadias
    • 1
  • Spiridon Nikolaidis
    • 1
  1. 1.Section of Electronics and Computers, Department of PhysicsAristotle University of ThessalonikiThessalonikiGreece

Personalised recommendations