Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs
Due to their flexibility, increased logic density and low design costs, Field-Programmable Gate Arrays (FPGAs) have become a viable option for implementing many kinds of applications such as custom computing machines, rapid system prototyping, hardware emulation, IP verification and evaluation. This paper proposes an alternative approach that allows IP providers to deliver their IP to customers for functional evaluation before purchase, by mapping IP cores into SRAM-based FPGA logic and distributing them as a bitstream file for a particular device so that customers can use their FPGA boards to try-out the IP as a black-box, pre-verified design component. This paper also presents a simple hardware/software infrastructure and its prototype implementation that allows for seamless integration of hardware IP into an existing simulation environment. In addition, a case study is given to demonstrate the proposed approach and some security issues concerning bitstream-level IP distribution are also discussed.
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- 1.IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Std. 1149.1-1990 (May 1990) Google Scholar
- 2.Synopsys Inc., Guide to Smart Model Documentation (November 2003), http://www.synopsys.com/
- 3.Summit Design, Inc., Visual IP, http://www.summit-design.com/
- 4.Altera Corp. IP Megastore web site, http://www.altera.com/products/ip/design/ipm-design.html
- 5.Inventra IPX Version 1.1 for LeonardoSpectrum Altera Release, http://www.mentor.com/inventra/ipx/
- 6.Aptix Corp., IP Test Drive, http://www.eSoCverify.com
- 7.Dalpasso, M., Bogliolo, A., Benini, L.: Specification and Validation of distributed IP-based designs with JavaCAD. In: Proc. of Design, Automation and Test in Europe Conference & Exhibition, Munich, Germany, pp. 684–688 (January 1999)Google Scholar
- 8.Fin, A., Fummi, F.: A Web-CAD methodology for IP-core analysis and simulation. In: Proc. of the 37th Design Automation Conference, Los Angeles, California, USA, June 05-09, pp. 597–600 (2000)Google Scholar
- 9.Wen, H.-P., Lin, C.-Y., Lin, Y.-L.: Concurrent Simulation-based Remote IP Evaluation over the Internet for System-on-a-Chip Design. In: Proc. of International Symposium on Systems Synthesis, Montreal, Quebec, Canada, September 30-October 3, pp. 233–238 (2001)Google Scholar
- 10.Wirthlin, M.J., McMurtrey, B.: IP delivery for FPGAs using Applets and JHDL. In: Proc. of the 39th ACM/IEEE Design Automation Conference, New Orleans, Louisiana, USA, June 10-14, pp. 2–7 (2002)Google Scholar
- 11.Siripokarpirom, R., Mayer-Lindenberg, F.: Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-based Rapid Prototyping Boards. In: Proc. of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), Geneva, Switzerland, June 28-30 (2004) (to appear)Google Scholar
- 12.OPENCORES.ORG, AES Project, http://www.opencores.org/