Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor

  • C. J. Tavares
  • C. Bungardean
  • G. M. Matos
  • J. T. de Sousa
Conference paper

DOI: 10.1007/978-3-540-30117-2_36

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)
Cite this paper as:
Tavares C.J., Bungardean C., Matos G.M., de Sousa J.T. (2004) Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. In: Becker J., Platzner M., Vernalde S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg

Abstract

This paper proposes an architecture that combines a context-switching virtual configware/software SAT solver with an embedded processor to promote a tighter coupling between configware and software. The virtual circuit is an arbitrarily large clause pipeline, partitioned into sections of a number of stages (hardware pages), which can fit in the configware. The hardware performs logical implications, grades and select decision variables. The software monitors the data and takes care of the high-level algorithmic flow. Experimental results show speed-ups that reach up to two orders of magnitude in one case. Future improvements for addressing scalability and performance issues are also discussed.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • C. J. Tavares
    • 1
  • C. Bungardean
    • 1
  • G. M. Matos
    • 1
  • J. T. de Sousa
    • 1
  1. 1.INESC-ID/IST-Technical University of Lisbon/CoreworksLisboaPortugal

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