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High Throughput Serpent Encryption Implementation

  • Jesús Lázaro
  • Armando Astarloa
  • Jagoba Arias
  • Unai Bidarte
  • Carlos Cuadrado
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

Very high speed and small area hardware architectures of the Serpent encryption algorithm are presented in this paper. The Serpent algorithm was a submission to the National Institute of Technology (NIST) as a proposal for the Advanced Encryption Standard (FIPS-197). Although it was not finally selected, Serpent was considered very secure and with a high potential in hardware implementations. Among others, a fully pipelined Serpent architecture is described in this paper and when implemented in a Virtex-II X2C2000-6 FPGA device, it runs at a throughput of 40 Gbps.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Jesús Lázaro
    • 1
  • Armando Astarloa
    • 1
  • Jagoba Arias
    • 1
  • Unai Bidarte
    • 1
  • Carlos Cuadrado
    • 1
  1. 1.Escuela Superior de IngenierosUniversity of the Basque CountryBilbaoSpain

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