Power Analysis of an FPGA

Implementation of Rijndael: Is Pipelining a DPA Countermeasure?
  • François-Xavier Standaert
  • Sıddıka Berna Örs
  • Bart Preneel
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3156)


Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they have been successfully applied to different kinds of (unprotected) implementations of symmetric and public-key encryption schemes. However, most published attacks apply to smart cards and only a few publications assess the vulnerability of hardware implementations. In this paper we investigate the vulnerability of Rijndael FPGA (Field Programmable Gate Array) implementations to power analysis attacks. The design used to carry out the experiments is an optimized architecture with high clock frequencies, presented at CHES 2003. First, we provide a clear discussion of the hypothesis used to mount the attack. Then, we propose theoretical predictions of the attacks that we confirmed experimentally, which are the first successful experiments against an FPGA implementation of Rijndael. In addition, we evaluate the effect of pipelining and unrolling techniques in terms of resistance against power analysis. We also emphasize how the efficiency of the attack significantly depends on the knowledge of the design.


Smart Card Clock Cycle Field Programmable Gate Array Block Cipher Advance Encryption Standard 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Daemen, J., Rijmen, V.: The Design of Rijndael. AES – The Advanced Encryption Standard. Springer, Heidelberg (2001)Google Scholar
  2. 2.
    FIPS 197, Advanced Encryption Standard, Federal Information Processing Standard, NIST, U.S. Dept. of Commerce(November 26, 2001) Google Scholar
  3. 3.
    Ors, S.B., Gurkaynak, F., Oswald, E., Preneel, B.: Power-Analysis Attack on an ASIC AES implementation. In: The proceedings of ITCC 2004, Las Vegas, April 5-7 (2004)Google Scholar
  4. 4.
    Xilinx: Virtex 2.5V Field Programmable Gate Arrays Data Sheet,
  5. 5.
    Rabaey, J.M.: Digital Integrated Circuits. Prentice Hall International, Englewood Cliffs (1996)Google Scholar
  6. 6.
    Standaert, F.-X., Rouvroy, G., Quisquater, J.-J., Legat, J.-D.: Efficient implementation of rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 334–350. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  7. 7.
    Brier, E., Clavier, C., Olivier, F.: Optimal Statistical Power Analysis, IACR e-print archive 2003/152Google Scholar
  8. 8.
    Mc Daniel, L.T.: An Investigation of Differential Power Analysis Attacks on FPGAbased Encryption Systems, Master Thesis, Virginia Polytechnic Insitute and State University, May 29 (2003)Google Scholar
  9. 9.
    Kocher, P., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 398–412. Springer, Heidelberg (1999)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • François-Xavier Standaert
    • 1
  • Sıddıka Berna Örs
    • 2
  • Bart Preneel
    • 2
  1. 1.UCL Crypto Group, Laboratoire de MicroélectroniqueUniversité Catholique de LouvainLouvain-La-NeuveBelgium
  2. 2.Dept. ESAT/SCD-COSICKatholieke Universiteit LeuvenLeuven-HeverleeBelgium

Personalised recommendations