Reducing Power Consumption in Interconnection Networks by Dynamically Adjusting Link Width

  • M. Alonso
  • J. M. Martínez
  • V. Santonja
  • P. López
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3149)


The huge increase both in size and complexity of high-end multiprocessor systems has triggered their power consumption. Air or liquid cooling systems are needed, which, in turn, increases power consumption. Another important percentage of the consumption is due to the interconnection network.

In this paper, we propose a mechanism that dynamically reduces the available network bandwidth when traffic becomes low. Unlike other approaches that completely switch links off when they are not fully utilized, our mechanism is based on reducing their bandwidth by narrowing their width. As the topology of the network is not modified, the same routing algorithm can be used regardless of the power consumption level, which simplifies the router design.

By using this strategy, the consumption may be strongly reduced. In fact, the lower bound of this reduction is a design parameter of the mechanism. The price to pay is an increase in the message latency with low network loads.


Power Consumption Interconnection Network Power Saving Virtual Channel Reduce Power Consumption 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Dao, B.V., Duato, J., Yalamanchili, S.: Dynamically configurable message flow control for fault-tolerant routing. IEEE Trans. on Parallel and Distributed Systems 10(1), 7–22 (1999)CrossRefGoogle Scholar
  2. 2.
    Duato, J.: A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans. on Parallel and Distributed Systems 4(12), 1320–1331 (1993)CrossRefGoogle Scholar
  3. 3.
    Duato, J., López, P.: Performance evaluation of adaptive routing algorithms for k-ary ncubes. In: Parallel Computer Routing and Communication Workshop (May 1994)Google Scholar
  4. 4.
    Duato, J.: A theory of fault-tolerant routing in wormhole networks. IEEE Trans. on Parallel and Distributed Systems 10(1), 7–22 (1999)CrossRefGoogle Scholar
  5. 5.
    Kim, J., Horowitz, M.: Adaptive supply serial links with sub-1V operation and per-pin clock recovery. In: Int. Solid-State Circuits Conf. (February 2002)Google Scholar
  6. 6.
    Kim, E.J., et al.: Energy Optimization Techniques in Cluster Interconnects. In: Int. Symp. on Low Power Electronics and Design (August 2003)Google Scholar
  7. 7.
    López, P., Duato, J.: Deadlock-free adaptive routing algorithms for the 3D-torus: limitations and solutions. In: Parallel Architectures Languages Europe 1993 (June 1993)Google Scholar
  8. 8.
    Mellanox Technologies home page,
  9. 9.
    Patel, C., Chai, S., Yalamanchili, S., Schimmel, D.: Power constrained design of multiprocessor interconnection networks. In: Int. Conf. on Computer Design (October 1997)Google Scholar
  10. 10.
    Shang, L., Peh, L.-S., Jha, N.K.: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In: 9th Int. Symp. on High-Performance Computer Architecture (January 2003)Google Scholar
  11. 11.
    Soteriou, V., Peh, L.-S.: Dynamic Voltage Power Management for Power Optimization of Interconnection Networks Using On/Off Links. In: 11th Hot Interconnects (August 2003)Google Scholar
  12. 12.
    Wang, H.-S., Peh, L.-S., Malik, S.: A power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. In: 10th Hot Interconnects (August 2002)Google Scholar
  13. 13.
    Wang, H.-S., Zhu, X., Peh, L.-S., Malik, S.: Orion: A Power-Performance Simulator for Interconnection Networks. In: 35th Int. Symposium on Microarchitecture (November 2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • M. Alonso
    • 1
  • J. M. Martínez
    • 1
  • V. Santonja
    • 1
  • P. López
    • 1
  1. 1.DISCAUniversidad Politécnica de ValenciaValenciaSpain

Personalised recommendations