Synchronous Transfer Architecture (STA)

  • Gordon Cichon
  • Pablo Robelly
  • Hendrik Seidel
  • Emil Matúš
  • Marcus Bronzel
  • Gerhard Fettweis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and coarse-grain reconfigurable hardware. STA processors are modeled using a common machine description suitable for both compiler and core generator. The core generator is able to generate models in Lisa, System-C, and VHDL. A special emphasis is placed on the good synthesis of the generated VHDL model.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Gordon Cichon
    • 1
  • Pablo Robelly
    • 1
  • Hendrik Seidel
    • 1
  • Emil Matúš
    • 1
  • Marcus Bronzel
    • 1
  • Gerhard Fettweis
    • 1
  1. 1.Mobile Communcations ChairTU-DresdenDresdenGermany

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