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Compiler and System Techniques for soc Distributed Reconfigurable Accelerators

  • Joël Cambonie
  • Sylvain Guérin
  • Ronan Keryell
  • Loïc Lagadec
  • Bernard Pottier
  • Olivier Sentieys
  • Bernt Weber
  • Samar Yazdani
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

To answer new challenges, systems on chip need to gain flexibility and fpgas need to gain structure. We propose a general framework for SoC architectures and software tools in which different kind of processing units are programmed at high level. We show a reconfigurable unit suitable for this framework and we draw the outline of a super-compiler able to address such an architecture.

Keywords

Shared Memory Address Generator Automatic Parallelization Hierarchical Graph Control Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Joël Cambonie
    • 1
  • Sylvain Guérin
    • 2
  • Ronan Keryell
    • 2
  • Loïc Lagadec
    • 3
  • Bernard Pottier
    • 3
  • Olivier Sentieys
    • 4
  • Bernt Weber
    • 2
  • Samar Yazdani
    • 3
  1. 1.STMicroelectronics/MPU 
  2. 2.ENST-Bretagne/LIT 
  3. 3.Université de Bretagne Occidentale/A&S 
  4. 4.Université de Rennes 1/IRISA 

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