Dynamic Hardware Reconfigurations: Performance Impact for MPEG2

  • Elena Moscu Panainte
  • Koen Bertels
  • Stamatis Vassiliadis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

In this paper, we study the impact dynamic reconfiguration has on the performance of current reconfigurable technology. As a testbed, we use the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. We show for the MPEG2 encoder that a substantial overall performance improvement, up to 34 %, can be achieved when SAD, DCT and IDCT functions are executed on the reconfigurable hardware when the compiler anticipates and separates configuration from execution. This study also considers the impact inappropriate scheduling can have on the overall performance. We show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the compiler. Our experiments show that appropriate scheduling allows to exploit up to 97% of the maximal theoretical speedup.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., Guerrieri, R.: A VLIW Processor with Reconfigurable Instruction Set for Embedded Applications. In: In ISSCC Digest of Technical Papers, pp. 250–251 (2003)Google Scholar
  2. 2.
    Sima, M., Vassiliadis, S., Cotofana, S.D., van Eijndhoven, J.T.J., Vissers, K.: Field- Programmable Custom Computing Machines - A Taxonomy. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 79–88. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  3. 3.
    Becker, J.: Configurable Systems-on-Chip: Commercial and Academic Approaches. In: Proc. of 9th IEEE Int. Conf. on Electronic Circuits and Systems - ICECS, Dubrovnik, Croatia, pp.809–812 (2002)Google Scholar
  4. 4.
    Gokhale, M.B., Stone, J.M.: Napa C: Compiling for a Hybrid RISC/FPGA Architecture. In: Proceedings of FCCM, Napa Valley, CA, pp.126–137 (1998)Google Scholar
  5. 5.
    Rosa, A.L., Lavagno, L., Passerone, C.: Hardware/Software Design Space Exploration for a Reconfigurable Processor. In: Proc. of DATE, Munich, Germany, pp.570–575 (2003)Google Scholar
  6. 6.
    Ye, Z.A., Shenoy, N., Banerjee, P.: A C Compiler for a Processor with a Reconfigurable Functional Unit. In: ACM/SIGDA Symposium on FPGAs, Monterey, California, USA, pp.95–100 (2000)Google Scholar
  7. 7.
    Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN ρμ-Coded Processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275–285. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  8. 8.
    Vassiliadis, S., Gaydadjiev, G., Bertels, K., Moscu Panainte, E.: The Molen Programming Paradigm. In: Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, Samos, Greece, pp.1–7 (2003)Google Scholar
  9. 9.
    Moscu Panainte, E., Bertels, K., Vassiliadis, S.: Compiling for the Molen Programming Paradigm. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 900–910. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  10. 10.
  11. 11.
  12. 12.
    M.Mercaldi, Smith, M.D., Holloway, G.: The Halt Library. In: The Machine-SUIF Documentation Set, Hardvard University,Cambridge (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Elena Moscu Panainte
    • 1
  • Koen Bertels
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering LabDelft University of TechnologyThe Netherlands

Personalised recommendations