Advertisement

Integrating Model Checking and Theorem Proving in a Reflective Functional Language

  • Tom Melham
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2999)

Abstract

Forte is a formal verification system developed by Intel’s Strategic CAD Labs for applications in hardware design and verification. Forte integrates model checking and theorem proving within a functional programming language, which both serves as an extensible specification language and allows the system to be scripted and customized. The latest version of this language, called reFL ect , has quotation and antiquotation constructs that build and decompose expressions in the language itself. This provides combination of pattern-matching and reflection features tailored especially for the Forte approach to verification. This short paper is an abstract of an invited presentation given at the International Conference on Integrated Formal Methods in 2004, in which the philosophy and architecture of the Forte system are described and an account is given of the role of reFL ect in the system.

Keywords

Model Check Theorem Prove Hardware Design High Order Logic Functional Programming Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Aagaard, M.D., Jones, R.B., Seger, C.-J.H.: Lifted-fl: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. In: Bertot, Y., Dowek, G., Hirschowitz, A., Paulin, C., Théry, L. (eds.) TPHOLs 1999. LNCS, vol. 1690, pp. 23–340. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  2. 2.
    Barras, B.: Proving and Computing in HOL. In: Aagaard, M.D., Harrison, J. (eds.) TPHOLs 2000. LNCS, vol. 1869, pp. 17–37. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  3. 3.
    Berghofer, S., Nipkow, T.: Executing higher order logic. In: Callaghan, P., Luo, Z., McKinna, J., Pollack, R. (eds.) TYPES 2000. LNCS, vol. 2277, pp. 24–40. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  4. 4.
    Bjesse, P., Claessen, K., Sheeran, M., Singh, S.: Lava: Hardware design in Haskell. In: Functional Programming: International Conference, ICFP 1998, pp. 174–184. ACM Press, New York (1998)CrossRefGoogle Scholar
  5. 5.
    Church, A.: A Formulation of the Simple Theory of Types. Journal of Symbolic Logic 5, 56–68 (1940)zbMATHCrossRefMathSciNetGoogle Scholar
  6. 6.
    Gordon, M.J.C., Melham, T.F. (eds.): Introduction to HOL: A theorem proving environment for higher order logic. Cambridge University Press, Cambridge (1993)zbMATHGoogle Scholar
  7. 7.
    Grundy, J., Melham, T., O’Leary, J.: A Reflective Functional Language for Hardware Design and Theorem Proving, Research Report PRG-RR-03-16, Programming Research Group, Oxford University (October 2003)Google Scholar
  8. 8.
    Harper, R., MacQueen, D., Milner, R.: Standard ML, Report 86-2, University of Edinburgh, Laboratory for Foundations of Computer Science (1986)Google Scholar
  9. 9.
    Harrison, J.: Metatheory and Reflection in Theorem Proving: A Survey and Critique, Technical Report CRC-053, SRI Cambridge (1995)Google Scholar
  10. 10.
    Jones, R.B., O’Leary, J.W., Seger, C.-J.H., Aagaard, M.D., Melham, T.F.: Practical formal verification in microprocessor design. IEEE Design & Test of Computers 18(4), 16–25 (2001)CrossRefGoogle Scholar
  11. 11.
    Kaivola, R., Kohatsu, K.R.: Proof engineering in the large: Formal verification of the Pentium-4 floating-point divider. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 196–211. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  12. 12.
    Kaivola, R., Narasimhan, N.: Formal verification of the Pentium-4 multiplier. In: High-Level Design Validation and Test: 6th International Workshop, HLDVT 2001, pp. 115–122. IEEE Computer Society Press, Los Alamitos (2001)CrossRefGoogle Scholar
  13. 13.
    Kaufmann, M., Manolios, P., Moore, J.S. (eds.): Computer-Aided Reasoning: ACL2 Case Studies. Kluwer, Dordrecht (2000)Google Scholar
  14. 14.
    Matthews, J., Cook, B., Launchbury, J.: Microprocessor specification in Hawk. In: IEEE International Conference on Computer Languages, pp. 90–101. IEEE Computer Society Press, Los Alamitos (1998)Google Scholar
  15. 15.
    O’Leary, J., Zhao, X., Gerth, R., Seger, C.-J.H.: Formally Verifying IEEE Compliance of Floating-Point Hardware. Intel Technical Journal (First quarter, 1999), Available at developer.intel.com/technology/itj/
  16. 16.
    Seger, C.-J.H., Bryant, R.E.: Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories. Formal Methods in System Design 6(2), 147–189 (1995)CrossRefGoogle Scholar
  17. 17.
    Seger, C.-J.H., Jones, R.B., O’Leary, J.W., Aagaard, M.D., Barrett, C., Syme, D.: An Industrially Effective Environment for Formal Hardware Verification (submitted for publication)Google Scholar
  18. 18.
    Sheard, T.: Accomplishments and Research Challenges in Meta-Programming. In: Taha, W. (ed.) SAIG 2001. LNCS, vol. 2196, pp. 2–44. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  19. 19.
    Sheard, T., Peyton Jones, S.: Template Meta-Programming for Haskell. In: Chakravarty, M.T.M. (ed.) ACM SIGPLAN Haskell Workshop, pp. 1–16. ACM Press, New York (2002)CrossRefGoogle Scholar
  20. 20.
    Spirakis, G.: Leading-edge and future design challenges: Is the classical EDA ready? In: Design Automation: 40th ACM/IEEE Conference, DAC 2003, p. 416. ACM Press, New York (2003)Google Scholar
  21. 21.
    Taha, W., Sheard, T.: Multi-stage programming with explicit annotations. SIGPLAN Notices 32(12), 203–217 (2002)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Tom Melham
    • 1
  1. 1.Computing LaboratoryOxford UniversityOxfordEngland

Personalised recommendations