CC 2004: Compiler Construction pp 250-264 | Cite as

Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors

  • Emre Özer
  • Andy P. Nisbet
  • David Gregg
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2985)

Abstract

Application-specific logic can be generated with a balance and mix of functional units tailored to match an application’s computational requirements. The area and power consumption of application-specific functional units, registers and memory blocks is heavily dependent on the bit-widths of operands used in computations. The actual bit-width required to store the values assigned to a variable during execution of a program will not in general match the built-in C data types with fixed sizes of 8, 16, 32 and 64 bits. Thus, precious area is wasted if the built-in data type sizes are used to declare the size of operands. A novel stochastic bit-width approximation technique is introduced to estimate the required bit-width of integer variables using Extreme Value Theory. Results are presented to demonstrate reductions in bit-widths, area and power consumption when the probability of overflow/underflow occurring is varied from 0.1 to infinitesimal levels. Our experimental results show that the stochastic bit-width approximation results in overall 32% reduction in area and overall 21% reduction in the design power consumption on a FPGA chip for nine embedded benchmarks.

Keywords

Power Consumption Total Power Consumption Gumbel Distribution Custom Hardware FPGA Chip 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Stephenson, M., Babb, J., Amarasinghe, S.: Bitwidth Analysis with Application to Silicon Compilation. In: Proceedings of the ACM SIGPLAN 2000 Conference on Programming Language Design and Implementation (PLDI), Vancouver, BC (June 2000)Google Scholar
  2. 2.
    Razdan, R., Smith, M.D.: A High-Performance Microarchitecture with Hardware- Programmable Functional Units. In: Proc. 27th Ann. Int’l. Symp. Microarchitecture, San Jose, CA (December 1994)Google Scholar
  3. 3.
    Stefanovi, D., Martonosi, M.: On Availability of Bit-narrow Operations in Generalpurpose Applications. In: The 10th International Conference on Field Programmable Logic and Applications (August 2000)Google Scholar
  4. 4.
    Budiu, M., Sakr, M., Walker, K., Goldstein, S.C.: BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations. In: Bode, A., Ludwig, T., Karl, W.C., Wismüller, R. (eds.) Euro-Par 2000. LNCS, vol. 1900, p. 969. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  5. 5.
    Mahlke, S., Ravindran, R., Schlansker, M., Schreiber, R., Sherwood, T.: Bitwidth Cognizant Architecture Synthesis of Custom Hardware Accelerators. HPL-2001-209 Technical Report (August 2001)Google Scholar
  6. 6.
    Cao, Y., Yasuura, H.: Quality-Driven Design by Bitwidth Optimization for Video Applications. In: Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC 2003) (January 2003)Google Scholar
  7. 7.
    Gupta, R., Mehofer, E., Zhang, Y.: A Representation for Bit Section Based Analysis and Optimization. In: Horspool, R.N. (ed.) CC 2002. LNCS, vol. 2304, p. 62. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  8. 8.
    Celoxica, Handel-C Language Reference Manual, Version 3.1 (2002)Google Scholar
  9. 9.
    Brase, C.H., Brase, C.P.: Understanding Basic Statistics, 2nd edn. Houghton Mifflin Company (2001)Google Scholar
  10. 10.
    Kinnison, R.R.: Applied Extreme Value Statistics. Macmillan Publishing Company, New York (1985)Google Scholar
  11. 11.
    Reiss, R.D., Thomas, M.: Statistical Analysis of Extreme Values. Birkhäuser, Basel (1997)MATHGoogle Scholar
  12. 12.
    Cronquist, D.C., Franklin, P., Berg, S.G., Ebeling, C.: Specifying and Compiling Applications for RaPiD. Field-Programmable Custom Computing Machines (1998)Google Scholar
  13. 13.
    Frigo, J., Gokhale, M., Lavenier, D.: Evaluation of the Streams-C C-to-FPGA Compiler: An Application Perspective. In: 9th ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA (February 2001)Google Scholar
  14. 14.
    Draper, B.A., Böhm, A.P.W., Hammes, J., Najjar, W., Beveridge, J.R., Ross, C., Chawathe, M., Desai, M., Bins, J.: Compiling SA-C Programs to FPGAs: Performance Results. In: Schiele, B., Sagerer, G. (eds.) ICVS 2001. LNCS, vol. 2095, p. 220. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  15. 15.
    Wilson, R.P., French, R.S., Wilson, C.S., Amarasinghe, S., Anderson, J.M., Tjiang, S.W.K., Liao, S.W., Tseng, C.W., Hall, M.W., Lam, M.S., Hennessy, J.L.: SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers. Technical. Report, Computer Systems Laboratory, Stanford University, CA, USA (1994)Google Scholar
  16. 16.
    Xilinx, Xilinx Virtex-II Architecture Manual (September 2002)Google Scholar
  17. 17.
    Fang, C.F., Rutenbar, R., Peuschel, M., Chen, T.: Toward Efficient Static Analysis of Finite-Precision Effects in DSP Applications via Affine Arithmetic Modeling. In: Design Automation Conference (2003)Google Scholar
  18. 18.
    Kim, S., Kum, K., Sung, W.: Fixed-point Optimization Utility for C and C++ Based Digital Signal Processing Programs. IEEE Trans. on Circuits and Systems 45(11) (November 1998)Google Scholar
  19. 19.
    Willems, M., Bürsgens, V., Keding, H., Grötker, T., Meyr, H.: System Level Fixed-point Design Based on An Interpolative Approach. In: Proc. 34th Design Automation Conference (June 1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Emre Özer
    • 1
  • Andy P. Nisbet
    • 1
  • David Gregg
    • 1
  1. 1.Department of Computer ScienceTrinity CollegeDublinIreland

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