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Accurate Cache and TLB Characterization Using Hardware Counters

  • Jack Dongarra
  • Shirley Moore
  • Philip Mucci
  • Keith Seymour
  • Haihang You
Conference paper
  • 575 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3038)

Abstract

We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions.

Keywords

Cache Size Array Size Data Cache Page Size Cache Associativity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Jack Dongarra
    • 1
  • Shirley Moore
    • 1
  • Philip Mucci
    • 1
  • Keith Seymour
    • 1
  • Haihang You
    • 1
  1. 1.Innovative Computing LaboratoryUniversity of TennesseeKnoxvilleUSA

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