Configurable Microprocessor Array for DSP Applications

  • Oleg Maslennikow
  • Juri Shevtshenko
  • Anatoli Sergyienko
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3019)

Abstract

The configurable microprocessor array for DSP applications is proposed, in which each cell is the microprocessor with RISC architecture, represented as a soft IP-core. This IP-core is generated automatically by the special soft-core generator, which is based on the approach to optimization of a microprocessor architecture for its further implementation in FPGA devices. Soft-core generator analyzes the executing program of each microprocessor of the array and eliminates all unused units from the resulting VHDL-model of the microprocessor. Therefore, hardware volume of each cell of this array is minimized, and is adapted to the used instruction subset. The soft-core generator provides both high throughput and minimized hardware volume with speedups the design process. It was probed in design the microprocessor array for solving the linear equation system with Toeplitz matrices.

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References

  1. 1.
    Villasenor, J., Hutchings, B.: The flexibility of configurable computing. IEEE Signal Processing Magazine 15, 67–84 (1998)CrossRefGoogle Scholar
  2. 2.
    Sergyienko, A., Maslennikov, O.: Implementation of Givens QR Decomposition in FPGA. In: Wyrzykowski, R., Dongarra, J., Paprzycki, M., Waśniewski, J. (eds.) PPAM 2001. LNCS, vol. 2328, pp. 453–459. Springer, Heidelberg (2002)Google Scholar
  3. 3.
    Lepekha, V., Sergyienko, A., Kaniewski, J.: VHDL-Model of Ultrafast Microcontroller 8051. In: Proc. 3-d Region. Conf. Reprogramowalne Uklady Cyfrowe, RUC 2000, Poland, pp. 35–41 (2000)Google Scholar
  4. 4.
    Maslennikov, O.: Configurable microcontroller array. In: Proc. of the 3-d Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC 2002, Warszaw, Poland, pp. 47–49 (2002)Google Scholar
  5. 5.
    Sergyienko, A.: VHDL for computer development. Kiev, Diasoft (2003) (in Russian)Google Scholar
  6. 6.
    Sergyienko, A., Kaniewski, J., Maslennikov, O., Wyrzykowski, R.: Mapping regular algorithms into processor arrays using software pipelining. In: Proc. of the 1-st Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC 1998, Poland, pp. 197–200 (1998)Google Scholar
  7. 7.
    Kanevski, J.S., Sergienko, A., Piech, H.: A Method for the Structural Synthesis of Pipelined Array Processors. In: Proc. of the 1-st Int. Conf. on Parallel Proc. and Appl. Math., PRAM 1994, Poland, pp. 100–109 (1994)Google Scholar
  8. 8.
    Kung, S.Y.: VLSI processor arrays. Prentice Hall, Englewood Cliffs (1988)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Oleg Maslennikow
    • 1
  • Juri Shevtshenko
    • 1
  • Anatoli Sergyienko
    • 1
  1. 1.Technical University of KoszalinKoszalinPoland

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