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Heterogeneous Approximate Multipliers: Architectures and Design Methodologies

  • Semeen Rehman
  • Bharath Srinivas Prabakaran
  • Walaa El-Harouni
  • Muhammad Shafique
  • Jörg Henkel
Chapter

Abstract

Multipliers are an integral block of a wide range of error-resilient applications like audio, image, and video processing, and machine learning. However, these multiplier architectures are computationally complex, and hence consume more power and occupy more area with long carry-adder trees when implementing multipliers with high bit-width. Approximate computing is an emerging design paradigm and is currently exploited to alleviate such area and power overheads, with slight/affordable degradation in the output quality of error-resilient application. An approximate multiplier architecture could either be approximated at the partial-product generation, accumulation, or summation stages. In this chapter, we focus on the different design aspects of energy-efficient approximate multipliers for both ASICs- and FPGAs-based systems.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Semeen Rehman
    • 1
  • Bharath Srinivas Prabakaran
    • 1
  • Walaa El-Harouni
    • 2
  • Muhammad Shafique
    • 1
  • Jörg Henkel
    • 3
  1. 1.Vienna University of Technology (TU Wien)ViennaAustria
  2. 2.Private ResearcherViennaAustria
  3. 3.Karlsruhe Institute of TechnologyKarlsruheGermany

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