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Approximate Multipliers and Dividers Using Dynamic Bit Selection

  • Soheil Hashemi
  • Sherief Reda
Chapter

Abstract

Within the approximate computing paradigm, approximate arithmetic logic design has received the most attention. The reason, simply the flexibility of such logic where basic building blocks, e.g., adders, multipliers, and dividers, can be utilized within a wide range of approximate data paths offering the benefits of approximate computing. Ideally, effective implementations of approximate arithmetic can readily be utilized within different applications without requiring application-level knowledge. In this chapter, a generic methodology for design of approximate arithmetic logic, namely approximate multipliers and approximate dividers, is proposed. The methodology has the desirable features that maintain an upper bound on maximum attainable error, and result in a zero-balanced error distribution averting error accumulation in consecutive processing. Furthermore, the proposed methodology is highly scalable to higher input sizes, and offers a wide range of accuracy hardware cost trade-offs. We evaluate our methodology with an approximate multiplier and approximate divider and highlight the significant benefits achieved, using both stand-alone and in application experiments.

Notes

Acknowledgements

The authors would like to thank Prof. R. Iris Bahar for her earlier contributions to this project [5, 6]. Compared to our previously published work [5, 6], this chapter provides a more holistic and integrated approach to the design of different approximate arithmetic logic. We also provide more discussions and examples on the working of the approximate methodology, and we provide additional experimental results. This work is partially supported by NSF grant 1420864.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Brown UniversityProvidenceUSA

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