Post-Silicon Fault Localization with Satisfiability Solvers

  • Georg WeissenbacherEmail author
  • Sharad Malik


This chapter covers techniques to localize faults in integrated circuits by means of automated satisfiability solvers. These techniques aim at identifying fault candidates for an erroneous execution trace by symbolically checking the consistency between the golden gate level model and the faulty behavior of the prototype chip. Contemporary satisfiability checkers, as well as the use of sliding windows, guarantee the scalability of our approach, which provides both spatial and temporal localization for general faults and is not restricted to a specific fault model.


Fault Candidates Erroneous Execution Minimal Correction Sets (MCS) Execution Window Scan Chain 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



Parts of this chapter are based on the habilitation of the first author [38] and describe joint work with Charlie Shucheng Zhu [27, 30, 35, 36]. The first author is supported by the Austrian National Research Network S11403-N23 (RiSE) and by the Vienna Science and Technology Fund (WWTF) through grant VRG11-005.


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© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.TU WienViennaAustria
  2. 2.Princeton UniversityPrincetonUSA

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