Advertisement

Nanopower SAR ADCs with Reference Voltage Generation

  • Maoqiang LiuEmail author
  • Kevin Pelzers
  • Rainier van Dommele
  • Arthur van Roermund
  • Pieter Harpe
Chapter

Abstract

This chapter targets low-power techniques for nanopower SAR ADCs with reference voltage generation. First of all, a 106nW 10b 80 kS/s SAR ADC with duty-cycled reference generation is presented, where a CMOS voltage reference, a duty-cycling block, and a LDO are integrated with the SAR ADC together. Furthermore, a low-power bidirectional comparator is utilized in the SAR ADC to reduce the power consumption. The reference-included SAR ADC achieves a FoM of 2.4fJ/conv.-step. Second, an energy-free DAC reset technique, “swap-to-reset,” is presented to deal with the large DAC reset energy in a SAR ADC, which is usually large compared with DAC conversion energy. In the prototype, the DAC energy consumption is reduced by one-third with “swap-to-reset” applied to the 2 MSBs. Finally, a low-power and area-efficient discrete-time reference driver is introduced. By calculating the energy consumption of each switching step, the DAC in a SAR ADC can be driven by a pre-charged decoupling capacitor compensated by a small auxiliary DAC. In the prototype, the SNDR/SFDR are improved by 2.7 dB/11.6 dB after enabling the 3b DAC compensation and the discrete-time reference driver only adds 10.8% and 10.1% to the power and chip area of the SAR ADC, respectively.

References

  1. 1.
    Borghetti F, Nielsen JH, Ferragina V, Malcovati P, Andreani P, Baschirotto A. A programmable 10b up-to-6MS/s SAR-ADC featuring constant-FoM with on-chip reference voltage buffers. In Proc. ESSCIRC, Sep. 2006, pp. 500–3.Google Scholar
  2. 2.
    Harikumar P, Wikner JJ. Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS. In Proc. IEEE ISCAS, May 2015, pp. 249–52.Google Scholar
  3. 3.
    Razavi B. Design of analog CMOS integrated circuits. Columbus: McGraw-Hill Education; 2000.Google Scholar
  4. 4.
    Vita GD, Iannaccone G. A sub-1-V, 10 ppm/°C, nanopower voltage reference generator. IEEE J Solid State Circuits. 2007;42(7):1536–42.Google Scholar
  5. 5.
    Magnelli L, Crupi F, Corsonello P, Pace C, Iannaccone G. A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference. IEEE J Solid State Circuits. 2011;46(2):465–74.CrossRefGoogle Scholar
  6. 6.
    Souri K, Chae Y, Ponomarev Y, Makinwa KAA. A precision DTMOST-based temperature sensor. ESSCIRC. 2011;12–16:279–82.Google Scholar
  7. 7.
    Vence A, Chittori C, Bosi A, Nani C. A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-way interleaved subranging SAR-∆∑ ADC with on-chip buffer in 28 nm CMOS. IEEE J Solid State Circuits. 2016;51(12):2951–62.CrossRefGoogle Scholar
  8. 8.
    Harpe P, Cantatore E, van Roermund A. An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR. ISSCC Dig Tech Papers, 2014, pp. 194–195.Google Scholar
  9. 9.
    Liu S, Shen Y, Zhu Z. A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching. IEEE Trans Circuits Syst I, Reg Papers. 2016;63(10):1616–27.MathSciNetCrossRefGoogle Scholar
  10. 10.
    Harpe P, Zhou C, van der Meijs NP, Wang X, Philips K, Dolmans G, de Groot H. A 26 μW 8-bit 10 MS/s asynchronous SAR ADC for low energy radios. IEEE J Solid State Circuits. 2011;46(7):1585–95.CrossRefGoogle Scholar
  11. 11.
    Liu C-C, Chang S-J, Huang G-Y, Lin Y-Z, Huang C-M. A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. Symp On VLSI Circuits, June 2010, pp. 241–2.Google Scholar
  12. 12.
    Tai H-Y, Hu Y-S, Chen H-W, Chen H-S. A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS. ISSCC Dig. Tech. Papers, Feb. 2014, pp. 196–7.Google Scholar
  13. 13.
    Liu M, Pelzers K, van Dommele R, van Roermund A, Harpe P. A 106nW 10 b 80 kS/s SAR ADC with duty-cycled reference generation in 65 nm CMOS. IEEE J Solid-State Circuits. 2016;51(10):2435–45.CrossRefGoogle Scholar
  14. 14.
    Liu M, van Roermund A, Harpe P. A 7.1-fJ/conversion-step 88-dB SFDR SAR ADC with energy-free “swap to reset”. IEEE J Solid State Circuits. 2017;52(11):2979–90.CrossRefGoogle Scholar
  15. 15.
    Liu M, van Roermund A, Harpe P. A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference. ESSCIRC, Sep. 2017, pp. 231–4.Google Scholar
  16. 16.
    Schemmert W, Zimmer G. Threshold-voltage sensitivity of ion-implanted m.o.s. transistors due to process variations. Electron Lett. 1974;10:151–2.CrossRefGoogle Scholar
  17. 17.
    Song B-S, Gray PR. Threshold-voltage temperature drift in ion-implanted MOS transistors. IEEE J Solid State Circuits. 1982;17(2):291–8.CrossRefGoogle Scholar
  18. 18.
    van Elzakker M, van Tuijl E, Geraedts P, Schinkel D, Klumperink EAM, Nauta B. A 10-bit charge-redistribution ADC consuming 1.9μW at 1MS/s. IEEE J Solid State Circuits. 2010;45(5):1007–15.CrossRefGoogle Scholar
  19. 19.
    Ivanov V, Brederlow R, Gerber J. An ultra-low power bandgap operational at supply from 0.75 V. IEEE J Solid State Circuits. 2012;47(7):1515–23.CrossRefGoogle Scholar
  20. 20.
    Osaki Y, Hirose T, Kuroki N, Numa M. 1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs. IEEE J Solid State Circuits. 2013;48(6):1530–8.CrossRefGoogle Scholar
  21. 21.
    Shrivastava A, Craig K, Roberts NE, Wentzloff DD, Calhoun BH. A 32nW bandgap reference voltage operational from 0.5V supply for ultra-low power systems. ISSCC Dig Tech Papers, Feb. 2015, pp. 94–5.Google Scholar
  22. 22.
    Chen Y-J, Hsieh C-C. A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain Quantizer in 90nm CMOS. IEEE Symp VLSI Circuits, Jun. 2014, pp. 35–6.Google Scholar
  23. 23.
    Liou C-Y, Hsieh C-C. A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge average switching DAC in 90nm CMOS. ISSCC Dig. Tech. Papers, Feb. 2013, pp. 280–1.Google Scholar
  24. 24.
    Harpe P, Cantatore E, van Roermund A. A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction. ISSCC Dig. Tech. Papers, Feb. 2013, pp. 270–1.Google Scholar
  25. 25.
    Harpe P, Gao H, van Dommele R, Cantatore E, van Roermund A. A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC. ISSCC Dig. Tech. Papers, Feb. 2015, pp. 382–3.Google Scholar
  26. 26.
    Chang Y-K, Wang C-S, Wang C-K. A 8-bit 500 kS/s low power SAR ADC for bio-medical application. ASSCC Dig Tech Papers, Nov. 2007, pp. 228–31.Google Scholar
  27. 27.
    Liu C-C, Chang S-J, Huang G-Y, Lin Y-Z. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid State Circuits. 2010;45(4):731–40.CrossRefGoogle Scholar
  28. 28.
    Hariprasath V, Guerber J, Lee S-H, Moon U-K. Merged capacitor switching based SAR ADC with highest switching energy-efficiency. Electron Lett. 2010;46(9):620–1.CrossRefGoogle Scholar
  29. 29.
    Lin Y-Z, Chang S-J, Shyu Y-T, Huang G-Y, Liu C-C. A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. ASSCC Dig. Tech. Papers, Nov. 2011, pp. 69–72.Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Maoqiang Liu
    • 1
    Email author
  • Kevin Pelzers
    • 1
  • Rainier van Dommele
    • 1
  • Arthur van Roermund
    • 1
  • Pieter Harpe
    • 1
  1. 1.Eindhoven University of TechnologyEindhovenThe Netherlands

Personalised recommendations