Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation
In this work, sub-threshold drain current model of Extended back Gate-Junctionless Transistor has been presented. Influence of fringing field from the gate over the extended source/drain region has also been included and verified with the ATLAS device simulation results. Superior gate controllability (compared to extended Source/drain conventional DG-JL transistor) and better device reliability (compared to schottky barrier source/drain DG-JL transistor) can be achieved using extended back gate in conventional DG-JL transistor. Device also shows superior Ion/Ioff ratio, sub-threshold slope, trans-conductance and device efficiency compared to conventional DG-JLT.
Abhineet Sharan (ENGS5560) would like to acknowledge Joint Science Academies Panel, Indian Academy of Sciences (IASc), Bangalore, India for selecting him under Science Academies’ Summer Research Fellowship Programme 2017.
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