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Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation

  • Vandana Kumari
  • Abhineet Sharan
  • Manoj SaxenaEmail author
  • Mridula Gupta
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 215)

Abstract

In this work, sub-threshold drain current model of Extended back Gate-Junctionless Transistor has been presented. Influence of fringing field from the gate over the extended source/drain region has also been included and verified with the ATLAS device simulation results. Superior gate controllability (compared to extended Source/drain conventional DG-JL transistor) and better device reliability (compared to schottky barrier source/drain DG-JL transistor) can be achieved using extended back gate in conventional DG-JL transistor. Device also shows superior Ion/Ioff ratio, sub-threshold slope, trans-conductance and device efficiency compared to conventional DG-JLT.

Notes

Acknowledgements

Abhineet Sharan (ENGS5560) would like to acknowledge Joint Science Academies Panel, Indian Academy of Sciences (IASc), Bangalore, India for selecting him under Science Academies’ Summer Research Fellowship Programme 2017.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Vandana Kumari
    • 1
    • 4
  • Abhineet Sharan
    • 2
  • Manoj Saxena
    • 3
    Email author
  • Mridula Gupta
    • 1
  1. 1.Department of Electronics ScienceUniversity of DelhiNew DelhiIndia
  2. 2.Electronics and Communication EngineeringPDPM Indian Institute of Information Technology, Design and ManufacturingJabalpurIndia
  3. 3.Department of ElectronicsDeen Dayal Upadhyaya College, University of DelhiNew DelhiIndia
  4. 4.Department of ElectronicsMaharaja Agrasen College, University of DelhiNew DelhiIndia

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