Investigation of Junctionless Transistor Based DRAM
In this work, we have investigated Double Gate junctionless transistor based capacitorless Dynamic Random Access Memory (1T-DRAM). The back gate is responsible for formation of an electrostatic potential well, while the front gate distinguishes the two states based on the charge stored at the back. The read operation is performed through drift-diffusion mechanism. The independent gate operation results in a retention time of 170 ms for gate length of 400 nm at 85 °C.
This work was supported by Department of Science and Technology Government of India, through Global Innovation and Technology Alliance under Grant no. GITA/DST/TWN/P-70/2015 and supported in part by the National Science Council of Taiwan, R.O.C., under Contact 104-2923-E-110-001-MY3.
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