Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology
In this work, the structure of a TFET device has been engineered such that it is not only better than most of the TFETs reported in literature, it’s performance is even better than the MOSFETs of the standard 45 nm CMOS technology. The device-level optimization has been discussed, in which, starting with a simple double-gate fully depleted TFET structure, the gradual improvement in device performance has been demonstrated such that the final ON current is comparable to that of the MOSFETs, while the OFF current remains at least three orders of magnitude lesser than the MOSFETs at the same 45 nm technology node. Optimization of the device structure has been carried out by studying the impact of various asymmetries in the device structure. This work is intentionally restricted only to the asymmetries which can be incorporated without any change in the standard process technology.
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