Independent Gate Operation of NAND Flash Memory Device with Improved Retention Characteristics

  • Pooja BoharaEmail author
  • S. K. Vishvakarma
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 215)


In this work we have analyzed Independent Gate (IG) operation of fully depleted double gate MOSFET to improve the retention characteristics and memory window of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory at relatively lower applied voltages. It is shown that biasing the back gate at negative potential during the reading operation significantly enhance the difference in the threshold voltages (Vth) of the programmed and erased state owing to strong electrostatic coupling between front and back gates. Results highlight that IG operation leads to 50% higher memory window in comparison with single gate mode. The retention characteristics at T = 358 K show that the memory window ~1.2 V is obtained after 10 years.


Flash memory SONOS Double gate MOSFETs 



This work was supported in part by the Council of Scientific and Industrial Research (CSIR), Government of India, under the Grant 22/0651/14/EMR-II and University Grants Commission, Government of India, through the Junior Research Fellowship (JRF) award to Pooja Bohara (Ref.: 4016/NET-June 2013).


  1. 1.
    K.H. Jang et al., Self-amplified dual gate charge trap flash memory for low-voltage operation. IEEE Electron Device Lett. 34(6), 756–758 (June 2013)ADSCrossRefGoogle Scholar
  2. 2.
    Yang (Larr) Yang, M. H. White, Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures. Solid-State Electron. 44(6), 949–958 (2000). ISSN 0038-1101Google Scholar
  3. 3.
    K. Miyaji, C. Hung, K. Takeuchi, Scaling trends and tradeoffs between short channel Effect and channel boosting characteristics in sub-20 nm bulk/silicon-on-insulator NAND flash memory. Jpn. J. Appl. Phys. 51, 04DD12 (Apr 2012)CrossRefGoogle Scholar
  4. 4.
    S.J. Choi, D.II. Moon, S. Kim, J.-H. Ahn, J.-S. Lee, J.-Y. Kim, Y.-K. Choi, Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate. IEEE Electron Device Lett. 32(5), 602–604 (May 2011)ADSCrossRefGoogle Scholar
  5. 5.
    Sentaurus TCAD Manuals, Synopsys Inc (Mountain view, CA, USA, 2016)Google Scholar
  6. 6.
    D. Gupta, S.K. Vishvakarma, Impact of LDD depth variations on the performance characteristics of SONOS NAND flash device. IEEE Trans. Device Mater. Reliab 16(3), 298–303 (Sept 2016)CrossRefGoogle Scholar
  7. 7.
    D. Gupta, S.K. Vishvakarma, Improved short-channel characteristics with long data retention time in extreme short-channel flash memory devices. IEEE Trans. Electron Devices 63(2), 668–674 (Feb 2016)ADSCrossRefGoogle Scholar
  8. 8.
    H.T. Lue, S.Y. Wang, E.K. Lai, Y.H. Shih, S.C. Lai, L.W. Yang, K.C. Chen, J. Ku, K.Y. Hsieh, R. Liu, C.Y. Lu, BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability, in IEEE International Electron Devices Meeting, Washington, DC, pp. 547–550 (2005)Google Scholar
  9. 9.
    J.-P. Colinge, SOI CMOS Technology, in Silicon-on-Insulator Technology: Materials to VLSI (Kluwer, New York, NY, USA, 1997)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Nanoscale Devices, VLSI Circuit and System Design Laboratory, Electrical EngineeringIndian Institute of Technology IndoreSimrol, IndoreIndia

Personalised recommendations