Independent Gate Operation of NAND Flash Memory Device with Improved Retention Characteristics
In this work we have analyzed Independent Gate (IG) operation of fully depleted double gate MOSFET to improve the retention characteristics and memory window of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory at relatively lower applied voltages. It is shown that biasing the back gate at negative potential during the reading operation significantly enhance the difference in the threshold voltages (Vth) of the programmed and erased state owing to strong electrostatic coupling between front and back gates. Results highlight that IG operation leads to 50% higher memory window in comparison with single gate mode. The retention characteristics at T = 358 K show that the memory window ~1.2 V is obtained after 10 years.
KeywordsFlash memory SONOS Double gate MOSFETs
This work was supported in part by the Council of Scientific and Industrial Research (CSIR), Government of India, under the Grant 22/0651/14/EMR-II and University Grants Commission, Government of India, through the Junior Research Fellowship (JRF) award to Pooja Bohara (Ref.: 4016/NET-June 2013).
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