Process Design for Fabrication of Multi-stack MEMS Capacitive Push-Pull Accelerometer Based on SOI Technology
The paper reports on process design for fabrication of a navigational grade ±30 g MEMS capacitive push-pull accelerometer based on SOI (Silicon-On-Insulator) technology using Pyrex Glass-Silicon-Pyrex Glass multi-stack. The accelerometer structure is fabricated by DWP (Dissolve Wafer Process) technique. The complete fabrication process and released structure results after two wafers process (SOI and Pyrex-Glass) step are discussed in this paper. After the release of accelerometer structure, another patterned glass wafer would be anodically bonded on top. The scheme of three wafer assembly of push-pull accelerometer is also proposed.
The Authors like to thanks Director SSPL for his kind permission to publish this paper. We acknowledge STARC (SITAR), Bangalore for fabrication support.
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