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Process Design for Fabrication of Multi-stack MEMS Capacitive Push-Pull Accelerometer Based on SOI Technology

  • Abha PanchalEmail author
  • Shankar Dutta
  • Ramjay Pal
  • Kapil Kumar Jain
  • D. K. Bhattacharya
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 215)

Abstract

The paper reports on process design for fabrication of a navigational grade ±30 g MEMS capacitive push-pull accelerometer based on SOI (Silicon-On-Insulator) technology using Pyrex Glass-Silicon-Pyrex Glass multi-stack. The accelerometer structure is fabricated by DWP (Dissolve Wafer Process) technique. The complete fabrication process and released structure results after two wafers process (SOI and Pyrex-Glass) step are discussed in this paper. After the release of accelerometer structure, another patterned glass wafer would be anodically bonded on top. The scheme of three wafer assembly of push-pull accelerometer is also proposed.

Notes

Acknowledgements

The Authors like to thanks Director SSPL for his kind permission to publish this paper. We acknowledge STARC (SITAR), Bangalore for fabrication support.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Abha Panchal
    • 1
    Email author
  • Shankar Dutta
    • 1
  • Ramjay Pal
    • 1
  • Kapil Kumar Jain
    • 1
  • D. K. Bhattacharya
    • 1
  1. 1.Solid State Physics LaboratoryTimarpurIndia

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