Advertisement

Simulation Study on Stability Aspect of Dual Metal Dual Dielectric Based TFET Architectures Against Temperature Variations

  • Upasana
  • Rakhi Narang
  • Manoj Saxena
  • M. GuptaEmail author
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 215)

Abstract

In this work simulation based investigation on stability aspect of Dual material Dual Dielectric based TFET configurations has been carried out. The device stability has been analyzed with variation in temperature using previously proposed architectures i.e. Dual Material Gate (DMG) TFET, Hetero-Dielectric (H-D) TFET and Dual Material Gate (DMG) Hetero-Dielectric (H-D) TFET. The simulation has been carried out using ATLAS device simulation software. For better clarity about the device sensitivity, circuit level analysis has been carried out using n-TFET inverter with resistive load. The time based study has been done where important figures of merit i.e. fall time delay and peak overshoot voltage and their dependence on operating temperature has been investigated.

Notes

Acknowledgements

Authors would like to thank Council of Scientific & Industrial Research (CSIR), India for providing necessary funding through the project (22(0724)/17/EMR-II) to pursue this research work.

References

  1. 1.
    S. Migita, K. Fukuda, Y. Morita, H. Ota, Experimental demonstration of temperature stability of Si-tunnel FET over Si-MOSFET, in IEEE Silicon Nanoelectronics Workshop (SNW), pp. 1–2 (2012)Google Scholar
  2. 2.
    R. Narang, M. Saxena, R.S. Gupta, M. Gupta, Immunity against temperature variability and bias point invariability in double gate tunnel field effect transistor. Microelectron. Reliab. 52, 1617–1620 (2012)CrossRefGoogle Scholar
  3. 3.
    Atlas Users Manual, Device Simulation Software, Silvaco International, Santa Clara, CA, Version 5.14.0. R, 2018 Google Scholar
  4. 4.
    Upasana, R. Narang, M. Saxena, M. Gupta, Modeling and TCAD assessment for gate material and gate dielectric engineered TFET architectures: circuit-level investigation for digital applications. IEEE Trans. Electron Devices 62, 3348–3356 (2015)ADSCrossRefGoogle Scholar
  5. 5.
    Upasana, R. Narang, M. Saxena, M. Gupta, Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges, in 2nd IEEE International Conference on Devices, Circuits and Systems (ICDCS-2014), pp. 1–6 (2014)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Semiconductor Device Research Laboratory, Department of Electronic ScienceUniversity of DelhiNew DelhiIndia
  2. 2.Department of ElectronicsSri Venkateswara College, University of DelhiNew DelhiIndia
  3. 3.Department of ElectronicsDeen Dayal Upadhyaya College, University of DelhiNew DelhiIndia

Personalised recommendations