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Background and State of the Art

  • Ricardo Filipe Sereno Póvoa
  • João Carlos da Palma Goes
  • Nuno Cavaco Gomes Horta
Chapter

Abstract

This chapter presents the background and the state of the art in the broad field of single-stage amplifiers, providing the context of the work developed. The performance metrics considered in this work are defined and detailed, namely, low-frequency gain, gain-bandwidth product, energy-efficient figure of merit, input-referred noise, and offset voltage. Moreover, notions on stability and frequency compensation are given. Operational amplifiers and operational transconductance amplifier topologies are explored, and dynamic amplification is addressed. The background and initial considerations are presented in Sect. 2.1; an overview on amplifiers, namely, single-stage architectures, is presented in Sect. 2.2; the important performance metrics considered throughout this work are described in Sect. 2.3; the operational transconductance amplifier is described in Sect. 2.4; and in the following sections, the most relevant architectures of single-stage amplifiers are described: Sect. 2.5 addresses elementary cascode amplifiers; Sect. 2.6 presents the recycling folded-cascode amplifier; and finally, dynamic amplifiers and the corresponding theory are addressed in Sect. 2.7.

References

  1. 1.
    R. Assaad, J. Silva-Martinez, “The Recycling Folded-cascode: A General Enhancement of the Folded-Cascode Amplifier,” in IEEE Journal of Solid-State Circuits, Vol. 44, Issue 9, Page(s): 2535–2542, Sep. 2009. DOI: https://doi.org/10.1109/JSSC.2009.2024819.
  2. 2.
    M. Amourah, R. Geiger, “All Digital Transistors High Gain Operational Amplifier Using Positive-feedback Technique,” in IEEE International Symposium on Circuits and Systems (ISCAS), Page(s): 701–704, May 2002. DOI: https://doi.org/10.1109/ISCAS.2002.1009937.
  3. 3.
    J. Ko, et al., “D-Band Common-Base Amplifiers With Gain-boosting and Inter stage Self-Matching in 0.18-μm SiGe HBT Technology,” in IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 64, Issue 3, Page(s): 254–258, Mar. 2017. DOI: https://doi.org/10.1109/TCSII.2016.2561963.
  4. 4.
    Y. Zheng, C. Saavedra, “Feedforward-Regulated Cascode OTA for Gigahertz Applications,” in IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 55, Issue 11, Pages(s): 3373–3382, Dec. 2008. DOI: https://doi.org/10.1109/TCSI.2008.2001800.
  5. 5.
    M. Ahmadi, “A New Modeling and Optimization of Gain-Boosted Cascode Amplifier for High-Speed and Low-Voltage Applications,” in IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 53, Issue 3, Page(s): 169–173, Mar. 2006. DOI: https://doi.org/10.1109/TCSII.2005.858493.
  6. 6.
    J. Huijsing, “Operational Amplifiers: Theory and Design,” Second Edition, Springer, 2011. DOI: https://doi.org/10.1007/97894-007-0596-8.
  7. 7.
    T. Carusone, et al., “Analog Integrated Circuit Design,” Second Edition, Wiley, 2012. ISBN: 978-0470770108.Google Scholar
  8. 8.
    P. Allen, D. Holberg, “CMOS Analog Circuit Design,” Second Edition, Oxford, 2002. ISBN: 9780195116441.Google Scholar
  9. 9.
    B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2000. ISBN: 978-0072380323.Google Scholar
  10. 10.
    H. Uhrmann, et al., “Analog Filters in Nanometer CMOS,” Springer, 2014. ISBN: 978-3-642-38013-6.Google Scholar
  11. 11.
    R. Baker, “CMOS Circuit Design, Layout and Simulation,” Third Edition, Wiley, 2010. ISBN: 978-0-470-88132-3.Google Scholar
  12. 12.
    F. Maloberti, “Analog Design for CMOS VLSI Systems,” Springer, 2001. ISBN: 978-0-306-47952-6.Google Scholar
  13. 13.
    W. Sansen, “Analog Design Essentials,” Springer, 2006. ISBN: 978-0-387-25747-1.Google Scholar
  14. 14.
    P. Gray, et al., “Analysis and Design of Analog Integrated Circuits,” Fifth Edition, Wiley, 2009. ISBN: 9781118313091.Google Scholar
  15. 15.
    A. Sedra, K. Smith, “Microelectronic Circuits,” Sixth Edition, Oxford, 2009. ISBN: 978-0195323030.Google Scholar
  16. 16.
    K. Bult, G. Geelen, “A fast-settling CMOS op amp with 90 dB DC-gain and 116 MHz unity-gain frequency,” in IEEE International Solid-State Circuits Conference (ISSCC), Page(s): 108–109, Feb. 1990. DOI: https://doi.org/10.1109/ISSCC.1990.110152.
  17. 17.
    S. Zhang, et al., “Design of A Low-power, High Speed Op-amp for 10bit 300Msps Parallel Pipeline ADCs,” in International Conference on Integration Technology, Page(s): 504–507, Mar. 2007. DOI: https://doi.org/10.1109/ICITECHNOLOGY.2007.4290367.
  18. 18.
    L. Su, Y. Qui, “Design of a Fully Differential Gain-Boosted Folded-Cascode Op Amp with Settling Performance Optimization,” in IEEE Conference on Electron Devices and Solid-State Circuits, Page(s): 441–444, Dec. 2005. DOI: https://doi.org/10.1109/EDSSC.2005.1635302.
  19. 19.
    Y. Li, et al., “Transconductance enhancement method for operational transconductance amplifiers,” in Electronics Letters, Vol. 46, Issue 19, Page(s): 1321–1323, Sep. 2010. DOI: https://doi.org/10.1049/el.2010.1575.
  20. 20.
    M. Ahmed, et al., “An Improved Recycling Folded-cascode Amplifier with Gain-boosting and Phase Margin Enhancement,” in IEEE International Symposium on Integrated Circuits (ISCAS), Page(s): 2473–2476, May 2015. DOI: https://doi.org/10.1109/ISCAS.2015.7169186.
  21. 21.
    S. Zabihian, R. Lofti, “Ultra-Low-Voltage, Low-Power, High-Speed Operational Amplifiers Using Body-Driven Gain-Boosting Technique,” in IEEE International Symposium on Circuits and Systems (ISCAS), Page(s): 705–708, May 2007. DOI: https://doi.org/10.1109/ISCAS.2007.377906.
  22. 22.
    M. Fallah, H. Naimi, “A Novel Low Voltage, Low Power and High Gain Operational Amplifier Using Negative Resistance and Self Cascode Transistors,” in International Journal of Engineering Transactions C: Aspects, Vol. 26, Issue 3, Page(s): 303–308, 2013.Google Scholar
  23. 23.
    S. Enche, et al., “A CMOS Single-Stage Fully Differential Folded-cascode Amplifier Employing Gain-boosting Technique,” in IEEE International Symposium on Integrated Circuits (ISIC), Page(s): 234–237, Dec. 2011. DOI: https://doi.org/10.1109/ISICir.2011.6131939.
  24. 24.
    X. Liu, J. McDonald, “Design of Single-Stage Folded-Cascode Gain-boost Amplifier for 14bit 12.5Ms/S Pipelined Analog-to-Digital Converter,” in IEEE International Conference on Software Engineering, Page(s): 622–626, Sep. 2012. DOI: https://doi.org/10.1109/SMElec.2012.6417222.
  25. 25.
    P. Yu, H. Lee, “A High-Swing 2-V CMOS Operational Amplifier with Replica-Amp Gain Enhancement,” in IEEE Journal of Solid-State Circuits, Vol. 28, Issue 12, Page(s): 1265–1272, Dec. 1993. DOI: https://doi.org/10.1109/4.261993.
  26. 26.
    E. Sackinger, W. Guggenbuhl, “A High-Swing High-Impedance MOS Cascode Circuit,” in IEEE Journal of Solid-State Circuits, Vol. 25, Issue 1, Page(s): 289–298, Feb. 1990. DOI: https://doi.org/10.1109/4.50316.
  27. 27.
    K. Bult, G. Geelen, “A fast-settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,” in IEEE Journal of Solid-State Circuits, Vol. 25, Issue 6, Page(s): 1379–1384, Dec. 1990. DOI: https://doi.org/10.1109/4.62165.
  28. 28.
    B. Alizadeh, A. Dadashi, “An Enhanced Folded-cascode Op Amp in 0.18 μm CMOS Process with 67dB Dc Gain,” in IEEE Faible Tension Faible Consommation (FTFC), Page(s): 87–90, May 2011. DOI: https://doi.org/10.1109/FTFC.2011.5948926.
  29. 29.
    M. Copeland, J. Rabaey, “Dynamic Amplifiers for MOS Technology,” in Electronics Letters, Vol. 15, Page(s): 301–302, May 1979. DOI: https://doi.org/10.1049/el:19790214.
  30. 30.
    B. Hosticka, “Dynamic CMOS Amplifiers,” in IEEE Journal of Solid-State Circuits, Vol. 15, Issue 5, Page(s): 887–894, Oct. 1980. DOI: https://doi.org/10.1109/JSSC.1980.1051488.
  31. 31.
    B. Hosticka, et al., “Performance of Integrated Dynamic MOS Amplifiers,” in Electronics Letters, Vol. 17, Issue 8, Page(s): 298–300, Apr. 1981. DOI: https://doi.org/10.1049/el:19810209.
  32. 32.
    J. Jung, B. Razavi, “A 25-Gb/s 5-mW CMOS CDR/Deserializer,” in IEEE Journal of Solid-State Circuits, Vol. 48, Issue 3, Page(s): 684–697, Mar. 2013. DOI: https://doi.org/10.1109/JSSC.2013.2237692.
  33. 33.
    B. Verbruggen, et al., “A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS,” in IEEE Journal of Solid-State Circuits, Vol. 45, Issue 10, Page(s): 2080–2090, Oct. 2010. DOI: https://doi.org/10.1109/JSSC.2010.2061611.
  34. 34.
    M. Gandara, et al., “A Pipelined SAR ADC Reusing the Comparator as Residue Amplifier,” in IEEE Custom Integrated Circuits Conference (CICC), Page(s): 1–4, Apr. 2017. DOI: https://doi.org/10.1109/CICC.2017.7993696.
  35. 35.
    M. Anthony, et al., “A process-scalable low-power charge-domain 13-bit pipeline ADC,” in IEEE Symposium on VLSI Circuits, Page(s): 222–223, Jun. 2008. DOI: https://doi.org/10.1109/VLSIC.2008.4586015.

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Ricardo Filipe Sereno Póvoa
    • 1
  • João Carlos da Palma Goes
    • 2
  • Nuno Cavaco Gomes Horta
    • 1
  1. 1.Instituto de Telecomunicações, Instituto Superior Técnico, Universidade de LisboaLisboaPortugal
  2. 2.UNINOVA, Faculdade de Ciências e Tecnologia, Universidade Nova de LisboaLisboaPortugal

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