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Formal and Virtual Multi-level Design Space Exploration

  • Letitia W. Li
  • Daniela Genius
  • Ludovic Apvrille
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 880)

Abstract

With the growing complexity of embedded systems, a systematic design process and tool are vital to help designers assure that their design meets specifications. The design of an embedded system evolves through multiple modeling phases, with varying levels of abstraction. A modeling toolkit should also support the various evaluations needed at each stage, in the form of simulation, formal verification, and performance evaluation. This chapter introduces our model-based engineering process with the supporting toolkit TTool, with two main design stages occurring at a different level of abstraction. A system-level design space exploration selects the architecture and partitions functions into hardware and software. The subsequent software design phase then designs and assesses the detailed functionality of the system, and evaluates the partitioning choices. We illustrate the design phases and supported evaluations with a Smart Card case study.

Keywords

Virtual prototyping Embedded systems System-level design Telecommunications 

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Télécom ParisTechUniversité Paris-SaclayBiotFrance
  2. 2.Sorbonne Universités, UPMC Paris 06, LIP6, CNRS UMR 7606ParisFrance
  3. 3.Institut VEDECOMVersaillesFrance

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