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FPGA Implementation of a Channelizer with 2048 Channels Utilizing USRP-SDR Platform for Satellite Communications

  • Simone Acciarito
  • Daniele Giardino
  • Gaurav Mani Khanal
  • Marco Re
  • Francesca Silvestri
  • Spanò Sergio
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 512)

Abstract

This paper presents an FPGA implementation of a channelizer based on digital filter bank with 2048 channels for satellite communications. The proposed architecture was simulated in Simulink and implemented on a Kintex-7 FPGA. The design was tested with a Universal Software Radio Peripheral (USRP).

Keywords

Channelizer Polyphase filter banks Software Defined Radio 

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Simone Acciarito
    • 1
  • Daniele Giardino
    • 1
  • Gaurav Mani Khanal
    • 1
  • Marco Re
    • 1
  • Francesca Silvestri
    • 1
  • Spanò Sergio
    • 1
  1. 1.Department of Electronic EngineeringUniversity of Rome Tor VergataRomeItaly

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