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The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes

  • Abdallah Cheikh
  • Gianmarco Cerutti
  • Antonio Mastrandrea
  • Francesco Menichelli
  • Mauro Olivieri
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 512)

Abstract

Internet-of-Things end-nodes demand low power processing platforms characterized by heterogeneous dedicated units, controlled by a processor core running multiple control threads. Such architecture scheme fits one of the main target application domain of the RISC-V instruction set. We present an open-source processing core compliant with RISC-V on the software side and with the popular Pulpino processor platform on the hardware side, while supporting interleaved multi-threading for IoT applications. The latter feature is a novel contribution in this application domain. We report details about the microarchitecture design along with performance data.

Keywords

Microprocessors RISC-V FPGA IoT Multi-threading 

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Abdallah Cheikh
    • 1
  • Gianmarco Cerutti
    • 1
  • Antonio Mastrandrea
    • 1
  • Francesco Menichelli
    • 1
  • Mauro Olivieri
    • 1
  1. 1.DIET, Sapienza University of RomeRomaItaly

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