Improving Robustness of a Real-Time Spectrum Sensing Application with the HARPA Run-Time Engine
As semiconductor technology nodes approach deca-nanometer dimensions, several phenomena threaten the binary correctness of a digital processor. Computer architectures typically enhance their designs with reliability, availability, and serviceability (RAS) schemes to correct such errors, frequently at the cost of extra clock cycles. This, in turn, leads to processor performance variability, which is undesirable for embedded consumer applications with hard quality of service (QoS) constraints. To mitigate performance variability, the HARPA cross-layer run-time engine (RTE) absorbs performance variability by means of dynamic voltage and frequency scaling (DVFS). This chapter provides an evaluation of the HARPA RTE mechanism for a real-time spectrum sensing application. As experimental setup, we use a DVFS-enabled embedded processor board, extended with the capability to generate temperature stress. To mitigate functional errors, a RAS mechanism is emulated in software. On this setup, we observe that temperature stress leads to recoverable functional errors, and that the RTE approach succeeds to mitigate performance variability due to aging and functional errors. Additionally, the RTE compensates performance variability for a dynamic application mix. In conclusion, the HARPA RTE is demonstrated to meet the robustness requirement in the presence of performance variability for an embedded workload, either caused by RAS performance variation or from dynamic application workloads.
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