Advertisement

Models of Architecture for DSP Systems

  • Maxime Pelcat
Chapter

Abstract

Over the last decades, the practice of representing digital signal processing applications with formal Models of Computation (MoCs) has developed. Formal MoCs are used to study application properties (liveness, schedulability, parallelism…) at a high level, often before implementation details are known. Formal MoCs also serve as an input for Design Space Exploration (DSE) that evaluates the consequences of software and hardware decisions on the final system. The development of formal MoCs is the design of increasingly complex applications requiring early estimates on a system’s functional behavior.

On the architectural side of digital signal processing system development, heterogeneous systems are becoming ever more complex. Languages and models exist to formalize performance-related information of a hardware system. They most of the time represent the topology of the system in terms of interconnected components and focus on time performance. However, the body of work on what we will call MoAs in this chapter is much more limited and less neatly delineated than the one on MoCs. This chapter proposes and argues a definition for the concept of an MoA and gives an overview of architecture models and languages that draw near the MoA concept.

Notes

Acknowledgements

I am grateful to François Berry and Jocelyn Sérot for their valuable advice and support during the writing of this chapter.

This work was partially supported by the CERBERO (Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments) Horizon 2020 Project, funded by the European Union Commission under Grant 732105.

References

  1. 1.
    Ammar M, Baklouti M, Pelcat M, Desnos K, Abid M (2016) Automatic generation of s-lam descriptions from uml/marte for the dse of massively parallel embedded systems. In: Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing 2015, Springer, pp 195–211Google Scholar
  2. 2.
    Bacivarov I, Haid W, Huang K, Thiele L (2018) Methods and tools for mapping process networks onto multi-processor systems-on-chip. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of Signal Processing Systems, 3rd edn, SpringerGoogle Scholar
  3. 3.
    Bellard F (2005) QEMU, a Fast and Portable Dynamic Translator. In: USENIX Annual Technical Conference, FREENIX Track, pp 41–46Google Scholar
  4. 4.
    Binkert N, Beckmann B, Black G, Reinhardt SK, Saidi A, Basu A, Hestness J, Hower DR, Krishna T, Sardashti S, others (2011) The gem5 simulator. ACM SIGARCH Computer Architecture News 39(2):1–7, URL http://dl.acm.org/citation.cfm?id=2024718 CrossRefGoogle Scholar
  5. 5.
    Castrillon Mazo J, Leupers R (2014) Programming Heterogeneous MPSoCs. Springer International Publishing, Cham, URL http://link.springer.com/10.1007/978-3-319-00675-8 CrossRefGoogle Scholar
  6. 6.
    Chen Y, Chen L (2013) Video compression. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of Signal Processing Systems, 2nd edn, SpringerGoogle Scholar
  7. 7.
    Eker J, Janneck JW, Lee E, Liu J, Liu X, Ludvig J, Neuendorffer S, Sachs S, Xiong Y, et al (2003) Taming heterogeneity-the ptolemy approach. Proceedings of the IEEE 91(1):127–144CrossRefGoogle Scholar
  8. 8.
    Faugere M, Bourbeau T, De Simone R, Gerard S (2007) Marte: Also an uml profile for modeling aadl applications. In: Engineering Complex Computer Systems, 2007. 12th IEEE International Conference on, IEEE, pp 359–364Google Scholar
  9. 9.
    Feiler PH, Gluch DP (2012) Model-based engineering with AADL: an introduction to the SAE architecture analysis & design language. Addison-WesleyGoogle Scholar
  10. 10.
    Feiler PH, Gluch DP, Hudak JJ (2006) The architecture analysis & design language (AADL): An introduction. Tech. rep., DTIC DocumentGoogle Scholar
  11. 11.
    Goglin B (2014) Managing the topology of heterogeneous cluster nodes with hardware locality (hwloc). In: High Performance Computing & Simulation (HPCS), 2014 International Conference on, IEEE, pp 74–81Google Scholar
  12. 12.
    Gondo M, Arakawa F, Edahiro M (2014) Establishing a standard interface between multi-manycore and software tools-SHIM. In: COOL Chips XVII, 2014 IEEE, IEEE, pp 1–3Google Scholar
  13. 13.
    Grandpierre T, Sorel Y (2003) From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations. In: Formal Methods and Models for Co-Design, 2003. MEMOCODE’03. Proceedings. First ACM and IEEE International Conference on, IEEE, pp 123–132Google Scholar
  14. 14.
    Ha S, Oh H (2013) Decidable dataflow models for signal processing: Synchronous dataflow and its extensions. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of Signal Processing Systems, 2nd edn, SpringerGoogle Scholar
  15. 15.
    Kahn G (1974) The semantics of a simple language for parallel programming. In Information Processing 74:471–475MathSciNetzbMATHGoogle Scholar
  16. 16.
    Keutzer K, Newton AR, Rabaey JM, Sangiovanni-Vincentelli A (2000) System-level design: orthogonalization of concerns and platform-based design. IEEE transactions on computer-aided design of integrated circuits and systems 19(12):1523–1543CrossRefGoogle Scholar
  17. 17.
    Kianzad V, Bhattacharyya SS (2004) CHARMED: A multi-objective co-synthesis framework for multi-mode embedded systems. In: Application-Specific Systems, Architectures and Processors, 2004. Proceedings. 15th IEEE International Conference on, IEEE, pp 28–40Google Scholar
  18. 18.
    Kienhuis B, Deprettere E, Vissers K, van der Wolf P (1997) An approach for quantitative analysis of application-specific dataflow architectures. In: Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on, IEEE, pp 338–349Google Scholar
  19. 19.
    Kienhuis B, Deprettere EF, Van Der Wolf P, Vissers K (2002) A methodology to design programmable embedded systems. In: Embedded processor design challenges, Springer, pp 18–37Google Scholar
  20. 20.
    Larsen M (2016) Modelling field robot software using aadl. Technical Report Electronics and Computer Engineering 4(25)Google Scholar
  21. 21.
    Lasnier G, Zalila B, Pautet L, Hugues J (2009) Ocarina: An environment for aadl models analysis and automatic code generation for high integrity applications. In: International Conference on Reliable Software Technologies, Springer, pp 237–250CrossRefGoogle Scholar
  22. 22.
    Lattner C, Adve V (2004) Llvm: A compilation framework for lifelong program analysis & transformation. In: Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, IEEE Computer Society, p 75Google Scholar
  23. 23.
    Lee EA (2006) The problem with threads. Computer 39(5):33–42CrossRefGoogle Scholar
  24. 24.
    Lee EA, Messerschmitt DG (1987) Synchronous data flow. Proceedings of the IEEE 75(9)CrossRefGoogle Scholar
  25. 25.
    Mallet F, André C (2008) Uml/marte ccsl, signal and petri nets. PhD thesis, INRIAGoogle Scholar
  26. 26.
    Mallet F, De Simone R (2009) Marte vs. aadl for discrete-event and discrete-time domains. In: Languages for Embedded Systems and Their Applications, Springer, pp 27–41Google Scholar
  27. 27.
    Multicore Association (2015) Software/Hardware Interface for Multicore/Manycore (SHIM) - http://www.multicore-association.org/workgroup/shim.php/ (accessed 03/2017)
  28. 28.
    OMG (2011) UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded Systems. Object Management Group, Needham, MAGoogle Scholar
  29. 29.
    Pelcat M, Nezan JF, Piat J, Croizer J, Aridhi S (2009) A system-level architecture model for rapid prototyping of heterogeneous multicore embedded systems. In: Proceedings of DASIP conferenceGoogle Scholar
  30. 30.
    Pelcat M, Mercat A, Desnos K, Maggiani L, Liu Y, Heulot J, Nezan JF, Hamidouche W, Menard D, Bhattacharyya SS (2017) Reproducible evaluation of system efficiency with a model of architecture: From theory to practice. Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)Google Scholar
  31. 31.
    Pimentel AD (2017) Exploring exploration: A tutorial introduction to embedded systems design space exploration. IEEE Design & Test 34(1):77–90MathSciNetCrossRefGoogle Scholar
  32. 32.
    Renfors M, Juntti M, Valkama M (2018) Signal processing for wireless transceivers. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of Signal Processing Systems, 3rd edn, SpringerGoogle Scholar
  33. 33.
    SAE International (2012) Architecture analysis and design language (aadl) - http://standards.sae.org/as5506c/ (accessed 03/2017)
  34. 34.
    Shekhar R, Walimbe V, Plishker W (2013) Medical image processing. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J (eds) Handbook of Signal Processing Systems, 2nd edn, SpringerGoogle Scholar
  35. 35.
    Stevens A (2011) Introduction to AMBA 4 ACE and big.LITTLE Processing TechnologyGoogle Scholar
  36. 36.
    Texas Instruments (2015) 66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) - SPRS930. Texas Instruments, URL http://www.ti.com/lit/pdf/sprs866e (accessed 03/2017)
  37. 37.
    Van Roy P, et al (2009) Programming paradigms for dummies: What every programmer should know. New computational paradigms for computer music 104Google Scholar
  38. 38.
    Wolf M (2014) High-performance embedded computing: applications in cyber-physical systems and mobile computing. NewnesGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Institut PascalAubièreFrance
  2. 2.IETR/INSARennesFrance

Personalised recommendations