Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network

  • Kalindu HerathEmail author
  • Alok Prakash
  • Thambipillai Srikanthan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10824)


Modern FPGAs consist of millions of logic resources allowing hardware designers to map increasingly large designs. However, the design productivity of mapping large designs is greatly affected by the long runtime of FPGA CAD flow. To mitigate it, modular design methodology has been introduced in the past that allows designers to partition large designs into smaller modules and compile & test the modules individually before assembling them together to complete the compilation process. Automated decision making on placing these modules on FPGA, however, is a slow and tedious process that requires large database of pre-compiled modules, which are compiled on a large number of placement positions. To accelerate this placement process during modular designing, in this paper we propose an ANN based performance estimation technique that can rapidly suggest the best shape and location for a given module. Experimental results on legacy as well as state-of-the-art FPGA devices show that the proposed technique can accurately estimate the \(F_{max}\) of modules with an average error of less than 4%.


FPGA Floorplaning Modular design methodology Computer-aided designing 


  1. 1.
  2. 2.
  3. 3.
    Increasing Productivity with Quartus II Incremental Compilation.
  4. 4.
  5. 5.
  6. 6.
    Vivado Design Suite User Guide-Hierarchical Design.
  7. 7.
  8. 8.
    Coole, J., et al.: BPR: fast FPGA placement and routing using macroblocks. In: CODES+ISSS (2012)Google Scholar
  9. 9.
    Frangieh, T., et al.: A design assembly framework for FPGA back-end acceleration. Microprocess. Microsyst. 38, 889–898 (2014)CrossRefGoogle Scholar
  10. 10.
    Gort, M., et al.: Design re-use for compile time reduction in FPGA high-level synthesis flows. In: FPT (2014)Google Scholar
  11. 11.
    Gupta, S., et al.: CAD techniques for power optimization in Virtex-5 FPGAs. In: Custom Integrated Circuits Conference, CICC 2007. IEEE (2007)Google Scholar
  12. 12.
    Haroldsen, T., et al.: Rapid FPGA design prototyping through preservation of system logic: a case study. In: FPL (2013)Google Scholar
  13. 13.
    Herath, K., et al.: Communication-aware partitioning for energy optimization of large FPGA designs. In: GLSVLSI (2017)Google Scholar
  14. 14.
    Lavin, C., et al.: HMFlow: accelerating FPGA compilation with hard macros for rapid prototyping. In: FCCM (2011)Google Scholar
  15. 15.
    Lavin, C., et al.: Impact of hard macro size on FPGA clock rate and place/route time. In: FPL (2013)Google Scholar
  16. 16.
    Lee, K., et al.: Shape exploration for modules in rapid assembly workflows. In: ReConFig (2015)Google Scholar
  17. 17.
    Love, A., et al.: In pursuit of instant gratification for FPGA design. In: FPL (2013)Google Scholar
  18. 18.
    Ludwin, A., et al.: Efficient and deterministic parallel placement for FPGAs. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 16, 1–23 (2011)CrossRefGoogle Scholar
  19. 19.
    Mao, F., et al.: Dynamic module partitioning for library based placement on heterogeneous FPGAs. In: RTCSA (2017)Google Scholar
  20. 20.
    Murray, K.E., et al.: Titan: enabling large and complex benchmarks in academic CAD. In: 2013 23rd International Conference on Field Programmable Logic and Applications (FPL) (2013)Google Scholar
  21. 21.
    Pouchet, L.N.: Polybench: the polyhedral benchmark suite (2012). (2012)
  22. 22.
    Rabozzi, M., et al.: Floorplanning for partially-reconfigurable FPGA systems via mixed-integer linear programming. In: FCCM (2014)Google Scholar
  23. 23.
    Tessier, R.: Fast placement approaches for FPGAs. TODAES 7, 284–305 (2002)CrossRefGoogle Scholar
  24. 24.
    Trimberger, S.M.: Three ages of FPGAs: a retrospective on the first thirty years of FPGA technology. Proc. IEEE. 103, 3108–331 (2015)CrossRefGoogle Scholar
  25. 25.
    Vipin, K., Fahmy, S.A.: Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds.) ARC 2012. LNCS, vol. 7199, pp. 13–25. Springer, Heidelberg (2012). Scholar
  26. 26.
    Wirthlin, M., et al.: Future field programmable gate array (FPGA) design methodologies and tool flows. Technical report (2008)Google Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Nanyang Technological UniversitySingaporeSingapore

Personalised recommendations