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An FPGA/HMC-Based Accelerator for Resolution Proof Checking

  • Tim HansmeierEmail author
  • Marco Platzner
  • David Andrews
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10824)

Abstract

Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Paderborn UniversityPaderbornGermany
  2. 2.University of ArkansasFayettevilleUSA

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