An FPGA/HMC-Based Accelerator for Resolution Proof Checking

  • Tim HansmeierEmail author
  • Marco Platzner
  • David Andrews
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10824)


Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.


  1. 1.
    Babb, J., Frank, M., Agarwal, A.: Solving graph problems with dynamic computation structures. In: Proceedings of SPIE: High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, vol. 2914, pp. 225–236 (1996)Google Scholar
  2. 2.
    Biere, A.: Picosat essentials. J. Satisf. Boolean Model. Comput. (JSAT) 4, 75–97 (2008)zbMATHGoogle Scholar
  3. 3.
    Chatterjee, S., Mishchenko, A., Brayton, R., Kuehlmann, A.: On resolution proofs for combinational equivalence. In: 2007 44th ACM/IEEE Design Automation Conference, pp. 600–605, June 2007Google Scholar
  4. 4.
    Cook, S.A.: The complexity of theorem-proving procedures. In: Proceedings of the Third Annual ACM Symposium on Theory of Computing, STOC 1971, pp. 151–158. ACM, New York (1971)Google Scholar
  5. 5.
    Heule, M., Biere, A.: Proofs for satisfiability problems, vol. 55, pp. 1–22. College Publications (2015)Google Scholar
  6. 6.
    Hybrid Memory Cube Consortium: Hybrid memory cube specification 2.0 (2014)Google Scholar
  7. 7.
    Isenberg, T., Platzner, M., Wehrheim, H., Wiersema, T.: Proof-carrying hardware via inductive invariants. ACM Trans. Des. Autom. Electron. Syst. 22(4), 61:1–61:23 (2017)CrossRefGoogle Scholar
  8. 8.
    McMillan, K.L.: Interpolation and SAT-based model checking. In: Hunt, W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 1–13. Springer, Heidelberg (2003). Scholar
  9. 9.
    Nai, L., Hadidi, R., Sim, J., Kim, H., Kumar, P., Kim, H.: GraphPIM: enabling instruction-level PIM offloading in graph computing frameworks. In: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 457–468, February 2017Google Scholar
  10. 10.
    Pawlowski, J.T.: Hybrid memory cube (HMC). In: 2011 IEEE Hot Chips 23 Symposium (HCS), pp. 1–24, August 2011Google Scholar
  11. 11.
    Skliarova, I., de Brito Ferrari, A.: Reconfigurable hardware SAT solvers: a survey of systems. IEEE Trans. Comput. 53(11), 1449–1461 (2004)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Paderborn UniversityPaderbornGermany
  2. 2.University of ArkansasFayettevilleUSA

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